公开(公告)号：US5808341A

公开(公告)日：1998-09-15

申请号：US747933

申请日：1996-11-12

Applicant: Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

Inventor： Shigenobu Maeda ,  Yasuo Yamaguchi ,  Il Jung Kim ,  Yasuo Inoue ,  Shigeto Maegawa ,  Takashi Ipposhi

IPC: H01L21/762 ,  H01L21/82 ,  H01L27/118 ,  H01L27/12 ,  H01L29/786 ,  H01L29/00

CPC classification number: H01L21/76202 ,  H01L21/76264 ,  H01L27/11807 ,  H01L27/1203 ,  H01L21/76281 ,  H01L21/76291

Abstract: FS-isolated fields (10a, 10b), LOCOS-isolated fields (11c, 11d), FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can be provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

Abstract translation: FS隔离场（10a，10b），LOCOS隔离场（11c，11d），FS隔离场（10e，10f），LOCOS隔离场（11g，11h）和FS隔离场（10i） 这个命令。 因此，可以提供主布局，其中将具有被提供固定电位的体的SOI晶体管和具有不具有固定电位的体的SOI晶体管混合。

公开(公告)号：US5780352A

公开(公告)日：1998-07-14

申请号：US553801

申请日：1995-10-23

Applicant: Heemyong Park ,  Wen-Ling Margaret Huang ,  Juergen Foerstner ,  Marco Racanelli

Inventor： Heemyong Park ,  Wen-Ling Margaret Huang ,  Juergen Foerstner ,  Marco Racanelli

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76264 ,  H01L21/32 ,  H01L21/76281

Abstract: A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).

Abstract translation: 在绝缘体上硅（SOI）衬底（21）上形成隔离氧化物（30）的方法包括在SOI衬底（21）的硅层（24）的区域上设置掩模层（26,27） ）。 隔离氧化物（30）生长在硅层（24）的不同区域（28）中。 隔离氧化物（30）生长到硅层（24）内的深度（32）小于或等于硅层（24）的厚度（29）。 在去除掩模层（26,27）之后，隔离氧化物（30）进一步生长在硅层（24）的不同区域（28）中，使得隔离氧化物（30）与掩埋电绝缘层 （23）内。 埋入的电绝缘层（23）和隔离氧化物（30）电绝缘半导体器件（20）的有源区（43）。

公开(公告)号：US5726082A

公开(公告)日：1998-03-10

申请号：US670839

申请日：1996-06-28

Applicant: Chan Kwang Park ,  Yo Hwan Koh

Inventor： Chan Kwang Park ,  Yo Hwan Koh

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786 ,  H01L21/265

CPC classification number: H01L29/66772 ,  H01L21/76202 ,  H01L21/76264 ,  H01L29/78603 ,  H01L29/78606 ,  H01L21/76275 ,  H01L21/76281

Abstract: A semiconductor device having a silicon-on-insulator structure, and a method for fabricating the semiconductor device, wherein a thick silicon oxide film is formed on each side wall of an active silicon substrate, thereby obtaining an increased threshold voltage at the edge of the active silicon substrate. The semiconductor device includes a first silicon substrate, a first silicon oxide film formed over the first silicon substrate, a second silicon substrate on the first silicon oxide film, second silicon oxide films, respectively disposed on opposite side walls of the second silicon substrate, a gate oxide film formed on the second silicon substrate, a gate electrode formed over the gate oxide film, and source/drain impurity diffusion regions, respectively formed in portions of the second silicon substrate disposed at both sides of the gate electrode. An impurity doped region having a conduction type opposite to that of the second silicon substrate, is defined between each side wall of the second silicon substrate and each corresponding second silicon oxide film in order to obtain an increased threshold voltage. Thus, the present invention easily controls threshold voltage, thereby improving in production yield.

Abstract translation: 一种具有绝缘体上硅结构的半导体器件及其半导体器件的制造方法，其中在有源硅衬底的每个侧壁上形成厚的氧化硅膜，从而在所述半导体器件的边缘处获得增加的阈值电压 活性硅衬底。 半导体器件包括第一硅衬底，在第一硅衬底上形成的第一氧化硅膜，在第一氧化硅膜上的第二硅衬底，分别设置在第二硅衬底的相对侧壁上的第二氧化硅膜， 形成在第二硅衬底上的栅极氧化膜，形成在栅极氧化膜上的栅电极以及分别形成在设置在栅电极两侧的第二硅衬底的部分中的源/漏杂质扩散区。 在第二硅衬底的每个侧壁和每个对应的第二氧化硅膜之间限定具有与第二硅衬底的导电类型相反的导电类型的杂质掺杂区域，以获得增加的阈值电压。 因此，本发明容易控制阈值电压，从而提高了产量。

公开(公告)号：US5719426A

公开(公告)日：1998-02-17

申请号：US745135

申请日：1996-11-07

Applicant: Toshiaki Iwamatsu ,  Takashi Ipposhi

Inventor： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/76297 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76281

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between the element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

Abstract translation: 通过薄膜硅层的MESA隔离来形成半导体集成电路，其中晶体管特性根据晶体管形成区域的图案密度而不受影响。 通过MESA隔离隔离绝缘基板上的薄膜硅层，形成元件形成区域。 在元件形成区域之间的大距离的中间部分，厚厚地形成LOCOS氧化物膜，并且氧化物膜以相同的表面水平相邻地掩埋在LOCOS氧化物膜和元件形成区域之间，使得不存在步骤 类似的水平差。

公开(公告)号：US5681775A

公开(公告)日：1997-10-28

申请号：US559383

申请日：1995-11-15

Applicant: H. Bernhard Pogge

Inventor： H. Bernhard Pogge

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76283 ,  Y10S148/012

Abstract: A method of forming a SOI device layer on an oxide layer on top of a substrate is disclosed. The process involves using a device substrate of a first conductivity having a top device layer of a second conductivity. Optionally, a thin layer of silicon dioxide is formed on top of the device layer. A carrier substrate is selected with a surface layer of silicon dioxide. Patterns are etched into the device and carrier substrates to preselected depths and surface widths, in a roughly complementary manner. The etched surfaces present a slope which enables the easy assembly of the device substrate and carrier substrate, the depths of the complementary patterns are controlled by the dopant layer thickness, and the slopes of etched profile are determined by the crystallographic orientations of the silicon substrate. The device substrate is thinned away to leave the device layer over the carrier substrate, thereby forming a device layer on the carrier substrate, separated by a silicon dioxide layer.

Abstract translation: 公开了一种在衬底顶部的氧化物层上形成SOI器件层的方法。 该方法涉及使用具有第二导电性的顶部器件层的第一导电性的器件衬底。 任选地，在器件层的顶部上形成薄层的二氧化硅。 用二氧化硅的表面层选择载体衬底。 以大致互补的方式将图案蚀刻到装置和载体基底中以预选的深度和表面宽度。 蚀刻的表面呈现出能够容易地组装器件衬底和载体衬底的斜率，互补图案的深度由掺杂剂层厚度控制，并且蚀刻轮廓的斜率由硅衬底的晶体取向决定。 将器件衬底减薄以将器件层留在载体衬底上，从而在载体衬底上形成由二氧化硅层分隔开的器件层。

公开(公告)号：US5596205A

公开(公告)日：1997-01-21

申请号：US445144

申请日：1995-05-19

Applicant: Ronald E. Reedy ,  Mark L. Burgener

Inventor： Ronald E. Reedy ,  Mark L. Burgener

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/86 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H04Q9/00 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L28/20 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/76264 ,  H01L21/86 ,  H01L27/1112 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78657 ,  H01L21/76281 ,  Y02B60/50 ,  Y10S148/15 ,  Y10S438/967 ,  Y10S438/974 ,  Y10S438/977

Abstract: A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Abstract translation: 介绍了蓝宝石芯片上单个硅片上的高频无线通信系统。 该系统在蓝宝石芯片上的单个超薄硅上集成了模拟，数字（逻辑和存储器）和高射频电路。 器件采用常规体硅CMOS处理技术制造。 优点包括单芯片架构，卓越的高频性能，低功耗和成本有效的制造。

公开(公告)号：US5508211A

公开(公告)日：1996-04-16

申请号：US198911

申请日：1994-02-17

Applicant: Abraham Yee ,  Sheldon Aronowitz

Inventor： Abraham Yee ,  Sheldon Aronowitz

IPC: H01L21/265 ,  H01L21/762

CPC classification number: H01L21/26533 ,  H01L21/26506 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76281 ,  H01L21/76283

Abstract: An integrated circuit structure vertically isolated electrically from the underlying substrate is formed in/on a single crystal semiconductor substrate, such as a silicon semiconductor wafer, by first implanting the substrate with a sufficient dosage of noble gas atoms to inhibit subsequent recrystallization of the semiconductor lattice in the implanted region during subsequent annealing, resulting in the formation of an isolation layer comprising implanted noble gas atoms enmeshed with semiconductor atoms in the substrate which has sufficient resistivity to act as an isolation layer. The preferred noble gases used to form such isolation layers are neon, argon, krypton, and xenon. When neon atoms are implanted, the minimum dosage should be at least about 6.times.10.sup.15 neon atoms/cm.sup.2 to inhibit subsequent recrystallization of the silicon substrate. When argon atoms are implanted, the minimum dosage should be at least about 2.times.10.sup.15 argon atoms/cm.sup.2. When krypton is implanted, the minimum dosage should be at least about 6.times.10.sup.24 krypton atoms/cm.sup.2. The energy used for the implant should be sufficient to provide an average implant depth sufficient to form, after annealing, the noble gas isolation layer at a depth of at least about 0.5 microns from the surface.

Abstract translation: 通过首先用足够量的惰性气体原子注入衬底以抑制随后的半导体晶格的再结晶，在诸如硅半导体晶片的单晶半导体衬底中/之上形成与下面的衬底电垂直隔离的集成电路结构 在随后退火期间的注入区域中，导致形成隔离层，该隔离层包含与衬底中具有充分电阻率充当隔离层的半导体原子嵌入的惰性气体原子。 用于形成这种隔离层的优选稀有气体是氖，氩，氪和氙。 当植入氖原子时，最小剂量应为至少约6×10 15氖原子/ cm 2以抑制随后的硅衬底的再结晶。 当注入氩原子时，最小剂量应至少为约2×1015氩原子/ cm2。 当植入氪时，最小剂量应为至少约6×1024氪原子/ cm2。 用于植入物的能量应足以提供足够的平均植入深度，以在退火之后形成距离表面至少约0.5微米深度的惰性气体隔离层。

公开(公告)号：US5480832A

公开(公告)日：1996-01-02

申请号：US75514

申请日：1993-10-21

Applicant: Shoji Miura ,  Takayuki Sugisaka ,  Atsushi Komura ,  Toshio Sakakibara

Inventor： Shoji Miura ,  Takayuki Sugisaka ,  Atsushi Komura ,  Toshio Sakakibara

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/768 ,  H01L21/76

CPC classification number: H01L21/763 ,  H01L21/76264 ,  H01L21/76802 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S148/05 ,  Y10S148/135 ,  Y10S438/977

Abstract: An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO.sub.2 film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO.sub.2 film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO.sub.2 film used as a mask when forming the isolation trench is etched off using the polysilicon in the isolation trench and the silicon nitride film as an etching stopper. In this manner, since the SiO.sub.2 film used as a mask is etched off after filling the isolation trench with polysilicon, the oxide film for isolating between the substrates is not etched when removing the mask film. Moreover since the polysilicon is the isolation trench and the silicon nitride film act as an etching stopper when etching off the SiO.sub.2 film used as a mask, the oxide film for a pad existing thereunder and the insulating film formed on an inside wall of the trench can also be prevented from being etched and a flatness at an isolation trench area is not deteriorated.

Abstract translation: PCT No.PCT / JP92 / 01326 Sec。 371日期：1993年10月21日 102（e）日期1993年10月21日PCT提交1992年10月12日PCT公布。 公开号WO93 / 08596 日期：1993年04月29日。本发明的目的在于防止在SOI衬底中形成的隔离沟槽区域中的电平差引起的布线断裂或短路。 在绝缘基板上形成的SOI层的主表面上形成氧化膜，依次形成氮化硅膜和SiO 2膜，然后通过RIE到达绝缘基板的隔离沟槽 使用SiO 2膜作为掩模。 此后，通过热氧化在隔离沟槽的内壁上形成绝缘膜，隔离沟槽填充有多晶硅，在控制蚀刻的同时蚀刻多晶硅，使得隔离沟槽中的多晶硅的顶部保持较高 除去氮化硅膜的顶部，去除沉积在衬底表面上的多晶硅的额外部分，然后使用隔离沟槽中的多晶硅蚀刻掉形成隔离沟槽时用作掩模的SiO 2膜， 作为蚀刻停止层的氮化硅膜。 以这种方式，由于在用多晶硅填充隔离沟槽之后蚀刻用作掩模的SiO 2膜，因此在去除掩模膜时不会蚀刻用于隔离的氧化膜。 此外，由于多晶硅是隔离沟槽，并且氮化硅膜在蚀刻掉用作掩模的SiO 2膜时用作蚀刻阻挡层，所以存在于其上的垫的氧化膜和形成在沟槽的内壁上的绝缘膜 也防止蚀刻，并且隔离沟槽区域的平坦度不会劣化。

公开(公告)号：US5416043A

公开(公告)日：1995-05-16

申请号：US90400

申请日：1993-07-12

Applicant: Mark L. Burgener ,  Ronald E. Reedy

Inventor： Mark L. Burgener ,  Ronald E. Reedy

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H01L21/76

CPC classification number: H01L28/20 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/76264 ,  H01L27/1112 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78654 ,  H01L29/78657 ,  H01L21/76281

Abstract: A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. .vertline.V.sub.tn .vertline.=.vertline.V.sub.tp .vertline.).

Abstract translation: 公开了一种用于制备适于制造完全耗尽的场效应晶体管的蓝宝石硅晶片的工艺。 描述了在导通通道中具有最小寄生电荷的完全耗尽的场效应晶体管（FET）和制造其的工艺。 该器件制造并依赖于蓝宝石上的硅层，其具有有意引入导通沟道的最小电荷。 描述了N型和P型晶体管。 还描述了用于定义阈值电压的方法。 给出了器件的具体实例，包括用于阈值电压选项的具体材料选择。 描述了制造方法，包括基于蓝宝石上的超薄硅的优选实施方案。 可以使用常规硅技术来制造器件; 提出硅化和非硅化两种版本。 优点包括由基本材料性质确定的阈值电压; 高性能器件由于减少了载流子散射，低横向电场和消除了身体效应; 阈值电压几乎与温度无关; 由于减少或消除寄生效应造成建模的简单性; 设备和工艺简单; 易于扩展和用于N沟道和P沟道MOSFET（即| Vtn | = | Vtp |）的固有对称阈值电压的选项。

公开(公告)号：US5369050A

公开(公告)日：1994-11-29

申请号：US889953

申请日：1992-05-29

Applicant: Shinichi Kawai

Inventor： Shinichi Kawai

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/762 ,  H01L23/544 ,  H01L27/12 ,  H01L21/76

CPC classification number: H01L29/66772 ,  H01L21/76251 ,  H01L21/76264 ,  H01L23/544 ,  H01L21/76267 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76283 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002

Abstract: A method of fabricating a semiconductor device includes the steps of forming a semiconductor layer having a convex device area and a convex alignment mark on an insulating layer. The insulating layer around the alignment mark is etched using the alignment mark as a mask to thereby form a groove around the alignment mark. A mask pattern is aligned with the device using the alignment mark surrounded by the groove as a reference point. Consequently the alignment mark can be detected using the step contour provided by the groove. This makes alignment using the so-called direct alignment technique possible, and alignment precision is improved.

Abstract translation: 制造半导体器件的方法包括以下步骤：在绝缘层上形成具有凸形器件区域和凸形对准标记的半导体层。 使用对准标记作为掩模蚀刻对准标记周围的绝缘层，从而在对准标记周围形成槽。 使用由凹槽围绕的对准标记作为参考点将掩模图案与设备对准。 因此，可以使用由凹槽提供的阶梯轮廓来检测对准标记。 这使得可以使用所谓的直接对准技术进行对准，并且提高对准精度。