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    RELAXATION OSCILLATOR
    51.
    发明申请
    RELAXATION OSCILLATOR 有权
    放松振荡器

    公开(公告)号：US20130200956A1

    公开(公告)日：2013-08-08

    申请号：US13612795

    申请日：2012-09-12

    申请人： Keng-Jan HSIAO

    发明人： Keng-Jan HSIAO

    IPC分类号： H03K3/36

    CPC分类号： H03K5/153 ,  G01R19/10 ,  H03K3/0231 ,  H03K3/36 ,  H03K4/502 ,  H03K5/2472

    摘要： A relaxation oscillator is provided. A first current source provides a first current. A second current source provides a second current. A resistive element is coupled between the first current source and a ground. A capacitive element is coupled between the second current source and the ground. A comparator has a non-inverting input terminal, an inverting input terminal and an output terminal for outputting a compare result. A clock generator provides a clock signal according to the compare result. A switching unit alternately couples the non-inverting input terminal and the inverting input terminal of the comparator to the resistive element and the capacitive element according to the clock signal.

    摘要翻译： 提供张弛振荡器。 第一电流源提供第一电流。 第二电流源提供第二电流。 电阻元件耦合在第一电流源和地之间。 电容元件耦合在第二电流源和地之间。 比较器具有非反相输入端子，反相输入端子和用于输出比较结果的输出端子。 时钟发生器根据比较结果提供时钟信号。 开关单元根据时钟信号将比较器的非反相输入端子和反相输入端子交替耦合到电阻元件和电容元件。

    Dual-trigger low-energy flip-flop circuit
    52.
    发明授权
    Dual-trigger low-energy flip-flop circuit 有权

    公开(公告)号：US08487681B2

    公开(公告)日：2013-07-16

    申请号：US13033426

    申请日：2011-02-23

    申请人： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  G E (Francis) Yang

    发明人： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  G E (Francis) Yang

    IPC分类号： H03K3/356

    CPC分类号： H03K3/36 ,  H03K3/012 ,  H03K3/356121

    摘要： One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

    System and Method For Supporting Different Types of Oscillator Circuits
    53.
    发明申请
    System and Method For Supporting Different Types of Oscillator Circuits 有权
    支持不同类型振荡器电路的系统和方法

    公开(公告)号：US20120280842A1

    公开(公告)日：2012-11-08

    申请号：US13100656

    申请日：2011-05-04

    申请人： Kristopher Kevin Kaufman ,  John Wayne Simmons

    发明人： Kristopher Kevin Kaufman ,  John Wayne Simmons

    IPC分类号： H03M1/00 ,  H03L7/00

    CPC分类号： H03K3/36 ,  H03B5/02 ,  H03B5/1206 ,  H03B5/1228 ,  H03B5/364 ,  H03B2200/0012 ,  H03B2200/0026 ,  H03B2200/0046 ,  H03F3/72 ,  H03K19/09429

    摘要： In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module.

    摘要翻译： 根据本公开的一些实施例，振荡器电路包括：与振荡器的第一端子相关联的第一焊盘和与振荡器的第二端子相关联的第二焊盘。 振荡器被配置为产生振荡信号并将振荡信号从第二终端传送到耦合到第二焊盘的时钟分配器。 振荡器电路还包括振荡器增益元件，其包括耦合到第一焊盘的输出节点和耦合到第二焊盘的输入节点。 振荡器电路还包括耦合到第一焊盘的数模转换器（DAC）。 振荡器电路还包括耦合到增益元件的开关电路。 开关电路被配置为当振荡器包括谐振器时启用增益元件，并且当振荡器包括电压控制的振荡模块时禁用增益元件。

    PULSE OUTPUT CIRCUIT, SHIFT REGISTER, AND DISPLAY DEVICE
    54.
    发明申请
    PULSE OUTPUT CIRCUIT, SHIFT REGISTER, AND DISPLAY DEVICE 有权
    脉冲输出电路，移位寄存器和显示设备

    公开(公告)号：US20080258998A1

    公开(公告)日：2008-10-23

    申请号：US11871704

    申请日：2007-10-12

    申请人： Hiroyuki MIYAKE

    发明人： Hiroyuki MIYAKE

    IPC分类号： G09G3/10 ,  G11C19/00 ,  H03K3/00

    CPC分类号： H01L27/1251 ,  G09G2310/0267 ,  G09G2310/0275 ,  G11C19/00 ,  G11C19/184 ,  H01L27/1222 ,  H01L27/124 ,  H03K3/36

    摘要： An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.

    摘要翻译： 目的是抑制移位寄存器中的晶体管的阈值电压的变化，并且防止晶体管在非选择期间发生故障。 设置在移位寄存器中的脉冲输出电路有规律地向处于浮置状态的晶体管的栅电极提供电位，使得在不输出脉冲的非选择期间，栅电极导通。 此外，通过定期导通或关闭另一个晶体管来提供晶体管的栅电极的电位。

    Logic circuit using resonant-tunneling transistor
    56.
    发明授权
    Logic circuit using resonant-tunneling transistor 失效
    使用谐振隧道晶体管的逻辑电路

    公开(公告)号：US4849934A

    公开(公告)日：1989-07-18

    申请号：US918300

    申请日：1986-10-10

    申请人： Naoki Yokoyama ,  Toshihiko Mori

    发明人： Naoki Yokoyama ,  Toshihiko Mori

    IPC分类号： G11C11/36 ,  G11C11/39 ,  H03K3/36 ,  H03K23/00

    CPC分类号： B82Y10/00 ,  G11C11/36 ,  G11C11/39 ,  H03K23/00 ,  H03K3/36 ,  G11C2211/5614

    摘要： A logic circuit including a resonant-tunneling transistor having a superlattice containing at least one quantum well layer, and a constant current source operatively connected between a base and an emitter of the transistor and supplying a constant current to said base. The transistor has a differential negative-resistance characteristic with at least one resonant point in a relationship between a current flowing in the base and a voltage between the base and emitter, and having at least two stable base current values at both sides of the resonant point on the characteristic, defined by the changeable base.multidot.emitter voltage. By supplying the base.multidot.emitter voltage having an amplitude of at least two amplitudes corresponding to the stable base current values, the transistor holds data corresponding to the base.multidot.emitter voltage.

    摘要翻译： 一种包括具有包含至少一个量子阱层的超晶格的谐振隧道晶体管的逻辑电路，以及可操作地连接在所述晶体管的基极和发射极之间的恒流源，并向所述基极提供恒定电流。 晶体管具有差分负电阻特性，其具有在基极中流动的电流与基极和发射极之间的电压之间的关系中的至少一个谐振点，并且在谐振点的两侧具有至少两个稳定的基极电流值 基于特征，由可变的基极电压定义。 通过提供具有对应于稳定的基极电流值的至少两个幅度的幅度的基极发射器电压，晶体管保持对应于基极发射极电压的数据。

    Negative impedance transistor device
    57.
    发明授权
    Negative impedance transistor device 失效
    负阻抗晶体管器件

    公开(公告)号：US4028562A

    公开(公告)日：1977-06-07

    申请号：US587093

    申请日：1975-06-16

    申请人： Rainer Zuleeg

    发明人： Rainer Zuleeg

    IPC分类号： G01R31/26 ,  H01L27/07 ,  H03B7/06 ,  H03K3/021 ,  H03K3/354 ,  H03K3/36 ,  H03K17/60 ,  H03B17/00

    CPC分类号： H03K3/354 ,  G01R31/2621 ,  H01L27/0716 ,  H03B7/06 ,  H03K3/021 ,  H03K3/36

    摘要： Transistor device exhibiting negative resistance characteristics includes an enhancement mode insulated gate field effect transistor interacting with an integral bipolar transistor. The transistor device has a bulk region separated from a shallow substrate region by a pn-junction located in proximity to source and drain regions of the field effect transistor. The source region also serves as the emitter, the substrate region serves as the base, and the bulk region serves as the collector of the integral bipolar transistor wherein the substrate base is left floating. Normally, the collector of the bipolar transistor is connected to the gate of the field effect transistor, and a resistor of finite value is included in the gate circuit. Oscillator, astable multivibrator, gated oscillator, gated astable multivibrator, and bistable multivibrator circuits are illustratively constructed with the transistor device.

    摘要翻译： 具有负电阻特性的晶体管器件包括与整体双极晶体管相互作用的增强型绝缘栅场效应晶体管。 晶体管器件具有通过位于场效应晶体管的源极和漏极区附近的pn结与浅衬底区域分离的体区域。 源极区域还用作发射极，衬底区域用作基极，并且体区域用作整体双极晶体管的集电极，其中衬底基底悬空。 通常，双极型晶体管的集电极连接到场效应晶体管的栅极，栅极电路中包含有限值的电阻。 振荡器，不稳定的多谐振荡器，门控振荡器，门控的非稳态多谐振荡器和双稳态多谐振荡器电路用晶体管器件示意地构造。

    SEMICONDUCTOR DEVICE AND SELECTOR CIRCUIT
    60.
    发明申请
    SEMICONDUCTOR DEVICE AND SELECTOR CIRCUIT 有权

    公开(公告)号：US20170104488A1

    公开(公告)日：2017-04-13

    申请号：US15291677

    申请日：2016-10-12

    申请人： LAPIS Semiconductor Co., Ltd.

    发明人： Shigeru NAGATOMO

    IPC分类号： H03K19/0185 ,  H01L27/092

    CPC分类号： H03K19/018521 ,  H01L27/092 ,  H01L29/0684 ,  H03K3/356113 ,  H03K3/356165 ,  H03K3/36 ,  H03K17/223

    摘要： A semiconductor device includes a setting circuit and a reset circuit. The setting circuit includes a latch circuit having first and second inverters driven by a first power voltage whose level is fixed and a first transistor which is switched between an ON state and an OFF state on the basis of a level of a second power voltage whose level varies depending on a surrounding environment, and sets data corresponding to a reference voltage to the latch circuit in response to the first transistor being switched to the ON state. The reset circuit includes an N-type second transistor connected to an output of the first inverter and an input of the second inverter. The second transistor sets data corresponding to the reference voltage to the latch circuit in response to the second voltage being equal to or lower than a predetermined voltage value.