公开(公告)号：US09806733B1

公开(公告)日：2017-10-31

申请号：US15339200

申请日：2016-10-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Martin Kinyua

IPC分类号： H03M1/06 ,  H03M1/12 ,  G04F10/00 ,  H03M1/10 ,  H04N5/378

CPC分类号： H03M1/124 ,  G04F10/005 ,  H03M1/1023 ,  H03M1/164 ,  H03M1/502 ,  H04N5/378

摘要： An analog-to-digital converter (ADC) circuit is configured to receive an analog input signal and convert the analog input signal to a digital output signal. The ADC circuit includes a first circuit that is configured to convert the analog input signal into a first digital signal that includes a first subset of bits of the digital output signal and further provide a residue signal based on the first digital signal; and a second circuit, coupled to the first circuit, and is configured to determine a discharging time duration by simultaneously amplifying and discharging the residue signal.

公开(公告)号：US20170310334A1

公开(公告)日：2017-10-26

申请号：US15507704

申请日：2015-09-02

申请人： University of Southern California

发明人： Shuo-Wei Chen

IPC分类号： H03M1/12 ,  H03M1/14 ,  H03M1/06 ,  H03M1/10 ,  H03M1/60 ,  H03M1/50

CPC分类号： H03M1/1245 ,  H03M1/0609 ,  H03M1/10 ,  H03M1/14 ,  H03M1/502 ,  H03M1/60

摘要： An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

公开(公告)号：US09729162B1

公开(公告)日：2017-08-08

申请号：US15223310

申请日：2016-07-29

申请人： SILICON LABORATORIES INC.

发明人： Wenhuan Yu ,  Abdulkerim L. Coban

IPC分类号： H03M1/06 ,  H03F3/45 ,  H03K5/1252 ,  H03M1/12 ,  H03H11/04 ,  H03M1/00

CPC分类号： H03M1/0617 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45636 ,  H03F3/45659 ,  H03F2200/267 ,  H03F2203/45022 ,  H03F2203/45222 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45512 ,  H03F2203/45526 ,  H03F2203/45528 ,  H03F2203/45591 ,  H03H11/04 ,  H03H11/0422 ,  H03H11/1213 ,  H03K5/1252 ,  H03M1/00 ,  H03M1/12 ,  H03M1/145 ,  H03M1/502

摘要： In one form, a signal chain circuit includes a signal chain processing circuit between an input for receiving a differential input signal having a first common-mode voltage, and an output for providing a differential output signal having a second, different common-mode voltage. It includes an amplifier with a differential output stage coupled to a differential input stage and having positive and negative output terminals forming its output, and positive and negative feedback terminals. The differential output stage provides a first voltage drop between the positive output terminal and the positive feedback terminal, and a second voltage drop between the negative output terminal and the negative feedback terminal. The common-mode feedback circuit regulates a common-mode voltage between the positive and negative feedback terminals to the second common-mode voltage. In another form, an analog-to-digital converter includes a range extending logic circuit to extend the range of a ring oscillator based analog-to-digital converter.

公开(公告)号：US20170187978A1

公开(公告)日：2017-06-29

申请号：US15455270

申请日：2017-03-10

申请人： OLYMPUS CORPORATION

发明人： Yoshio Hagihara

IPC分类号： H04N5/376 ,  H04N5/3745 ,  H03M7/30 ,  H03K5/15 ,  H03M1/20

CPC分类号： H04N5/3765 ,  H03K5/15066 ,  H03M1/123 ,  H03M1/20 ,  H03M1/502 ,  H03M1/56 ,  H03M7/30 ,  H04N5/3745 ,  H04N5/378

摘要： An encoding circuit includes a clock generating unit having a delay circuit in which n (n is a power of 2) delay units are connected together a latch unit configured to latch the plurality of delayed signals; and an encoding unit configured to encode state of each of the plurality of delayed signals, wherein the encoding unit encodes the state of each of the plurality of delayed signals by performing: a first operation of determining a position at which logic states of two or more delayed signals in a signal group change from High to Low, a second operation of determining a position at which logic states of two or more delayed signals in the signal group change from Low to High, and a third operation of determining that logic states of two or more signals including at least one delayed signal in the signal group are predetermined states.

公开(公告)号：US09483028B1

公开(公告)日：2016-11-01

申请号：US15099460

申请日：2016-04-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Martin Kinyua

IPC分类号： H03M1/06 ,  G04F10/00 ,  H03M1/12 ,  H03M1/10

CPC分类号： H03M1/124 ,  G04F10/005 ,  H03M1/1023 ,  H03M1/164 ,  H03M1/502 ,  H04N5/378

摘要： An analog-to-digital converter (ATC) circuit includes a current source; a first amplifier coupled to the current source through a first discharging switch; and a second amplifier coupled to the first amplifier through a second discharging switch; wherein the first amplifier is configured to receive a residue signal of an analog input signal, upon the first discharging switch being turned on, the first amplifier amplifies the residue signal to generate an output signal and simultaneously the current source discharges the residue signal, upon the second discharging switch being turned on, the second amplifier detects when the output signal equals zero so as to determine a discharging time duration of the output signal.

摘要翻译： 模拟 - 数字转换器（ATC）电路包括电流源; 第一放大器，通过第一放电开关耦合到电流源; 以及通过第二放电开关耦合到所述第一放大器的第二放大器; 其中所述第一放大器被配置为在所述第一放电开关导通时接收模拟输入信号的残留信号，所述第一放大器放大所述残留信号以产生输出信号，并且同时所述电流源对所述残留信号进行放电， 第二放大开关导通，第二放大器检测输出信号何时等于零，以便确定输出信号的放电持续时间。

公开(公告)号：US09204070B2

公开(公告)日：2015-12-01

申请号：US13064910

申请日：2011-04-26

申请人： Tomohiro Takahashi ,  Hiroki Ui ,  Junichi Inutsuka ,  Nozomu Takatori

发明人： Tomohiro Takahashi ,  Hiroki Ui ,  Junichi Inutsuka ,  Nozomu Takatori

IPC分类号： H04N5/335 ,  H04N5/378 ,  H04N5/3745 ,  H03M1/50 ,  H03M1/12 ,  H03M1/14 ,  H03M1/56 ,  H03M1/60

CPC分类号： H04N5/378 ,  H03M1/123 ,  H03M1/14 ,  H03M1/502 ,  H03M1/56 ,  H03M1/60 ,  H04N5/3745

摘要： An integrating A/D converter includes: a comparator comparing an input voltage to a reference voltage having a ramp waveform, a voltage value of which linearly varies with time; a higher-order bit counter starting operation or stopping operation triggered by inversion of an output signal of the comparator and outputting higher order bits by performing counting in a cycle of a clock signal; and a time-to-digital converter latching phase information of the clock signal corresponding to plural signals obtained by delaying an output signal of the comparator and decoding the latched values to output lower order bits having higher resolution than the clock cycle.

摘要翻译： 积分A / D转换器包括：比较输入电压与具有斜坡波形的参考电压的比较器，其电压值随时间线性变化; 通过比较器的输出信号的反相触发的高位位计数器启动操作或停止操作，并通过在时钟信号的周期中进行计数来输出高位位; 以及时间 - 数字转换器，其锁存与通过延迟比较器的输出信号而获得的多个信号相对应的时钟信号的相位信息，并对锁存的值进行解码以输出比时钟周期更高的分辨率的低阶位。

公开(公告)号：US20150212494A1

公开(公告)日：2015-07-30

申请号：US14681206

申请日：2015-04-08

申请人： IQ-Analog Corporation

发明人： Mikko Waltari

IPC分类号： G04F10/00 ,  H03M1/12

CPC分类号： G04F10/005 ,  H03M1/1295 ,  H03M1/50 ,  H03M1/502 ,  H03M1/60

摘要： A Traveling Pulse Wave Quantization method is provided for converting a time sensitive signal to a digital value. A first stop signal is delayed by a first time delay, a first plurality of times, to create a delayed first stop signal. A clock signal is delayed by a second time delay, a first plurality of times, to create a delayed clock signal first period. Each second time delay is associated with a corresponding first time delay, and the second time delay is greater than the first time delay. When the delayed first stop signal occurs before the delayed clock signal first period, a count of the delays is stopped and converted into a digital or thermometer value. An accurate resampled value is provided regardless of the duration in delay between the first stop signal and a second stop signal that is accepted after the first stop signal.

摘要翻译： 提供了一种将时间敏感信号转换为数字值的行波脉冲波量化方法。 第一停止信号被延迟第一时间延迟，第一次多次，以产生延迟的第一停止信号。 时钟信号被延迟第二时间延迟，第一次多次，以产生延迟的时钟信号第一周期。 每个第二时间延迟与对应的第一时间延迟相关联，并且第二时间延迟大于第一时间延迟。 当延迟的第一停止信号在延迟时钟信号第一周期之前发生时，延迟的计数被停止并转换成数字或温度计值。 无论第一停止信号和第一停止信号之后接受的第二停止信号的延迟持续时间如何，均提供精确的重采样值。

公开(公告)号：US09035227B2

公开(公告)日：2015-05-19

申请号：US13662596

申请日：2012-10-29

申请人： OLYMPUS CORPORATION

发明人： Takanori Tanaka ,  Susumu Yamazaki

IPC分类号： H01L27/00 ,  H04N5/335 ,  H03M1/34 ,  H04N5/376 ,  H03M1/50 ,  H03M1/12 ,  H04N5/378

CPC分类号： H04N5/3765 ,  H03M1/123 ,  H03M1/502 ,  H04N5/378

摘要： In this solid-state imaging device, an output signal of any one of a plurality of delay units that output signals of logic states in accordance with a level of a pixel signal is input to an input terminal of a latch circuit that latches a logic state of the output signal. A NAND circuit and an INV circuit stop until a control signal output timing at which a control signal in accordance with the level of the pixel signal is output, and operate after the control signal output timing. A switch circuit outputs the output signal of the one of the plurality of delay units through a signal line from an output terminal until the control signal output timing, and switches a connection at a latch timing after a predetermined time elapses from the control signal output timing such that the NAND circuit and the INV circuit latch the logic state of the output signal of the one of the plurality of delay units.

摘要翻译： 在该固态成像装置中，将根据像素信号的电平输出逻辑状态的信号的多个延迟单元中的任一个的输出信号输入到锁存逻辑状态的锁存电路的输入端子 的输出信号。 NAND电路和INV电路停止，直到输出根据像素信号的电平的控制信号的控制信号输出定时，并且在控制信号输出定时之后操作。 开关电路通过信号线从输出端子输出多个延迟单元中的一个延迟单元的输出信号，直到控制信号输出定时，并且在从控制信号输出定时经过预定时间之后的锁存定时处切换连接 使得NAND电路和INV电路锁存多个延迟单元之一的输出信号的逻辑状态。

公开(公告)号：US20150115925A1

公开(公告)日：2015-04-30

申请号：US14466399

申请日：2014-08-22

申请人： Kabushiki Kaisha Toshiba

发明人： Chen Kong Teh ,  Atsushi Suzuki

IPC分类号： H03M1/00 ,  H02M3/157 ,  H03M1/12

CPC分类号： H03M1/002 ,  G04F10/005 ,  H02M3/157 ,  H03M1/068 ,  H03M1/12 ,  H03M1/502

摘要： According to one embodiment, an A/D converter includes a first delay cell column in which a plurality of delay cells, to which a first bias current corresponding to a difference voltage between an input voltage and a reference voltage is supplied, is connected in series. The converter includes a second delay cell column in which a plurality of delay cells, to which a second bias current corresponding to a negative-phase difference voltage of the difference voltage is supplied, is connected in series. The converter includes an encoder unit configured to encode a difference value, in delay time of signal propagation, between the first delay cell column and the second delay cell column.

摘要翻译： 根据一个实施例，A / D转换器包括第一延迟单元列，其中提供与输入电压和参考电压之间的差分电压相对应的第一偏置电流的多个延迟单元串联连接 。 转换器包括第二延迟单元列，其中与供给差分电压的负相位差电压相对应的第二偏置电流的多个延迟单元串联连接。 转换器包括：编码器单元，被配置为在第一延迟单元列和第二延迟单元列之间对信号传播的延迟时间中的差值进行编码。

公开(公告)号：US20140354461A1

公开(公告)日：2014-12-04

申请号：US14267790

申请日：2014-05-01

申请人： Renesas Electronics Corporation

发明人： Takahiro Kawano

IPC分类号： H03M1/12

CPC分类号： H03M1/502

摘要： A semiconductor device includes an analog-digital converter circuit. The analog-digital converter circuit includes a delay cell array and an encoder. The delay cell array contains n number of serially-coupled delay cells, receives a reference clock signal, and utilizes an analog input signal as the power supply voltage for the delay cells in each stage. The encoder encodes an output signal from the delay cell in each stage for the delay cell array and outputs the encoded output signal as a digital output signal. The n number of delay cells includes delay quantities weighted for each delay cell. The encoder encodes the output signal of the delay cells in each stage for the delay cell array by weighting corresponding to the number of delay cell stage.

摘要翻译： 半导体器件包括模数转换器电路。 模拟数字转换器电路包括延迟单元阵列和编码器。 延迟单元阵列包含n个串联耦合延迟单元，接收参考时钟信号，并且利用模拟输入信号作为每个级中的延迟单元的电源电压。 编码器对来自延迟单元阵列的每个级中的延迟单元的编码器进行编码，并输出编码的输出信号作为数字输出信号。 n个延迟单元包括为每个延迟单元加权的延迟量。 编码器通过对应于延迟单元级数的加权，对延迟单元阵列的每个级中的延迟单元的输出信号进行编码。