公开(公告)号：US20240113943A1

公开(公告)日：2024-04-04

申请号：US17964367

申请日：2022-10-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Ioannis (Giannis) PATRONAS ,  Paraskevas BAKOPOULOS ,  Dimitrios SYRIVELIS ,  Elad MENTOVICH ,  Eitan ZAHAVI ,  Louis Bennie CAPPS, Jr. ,  Prethvi Ramesh KASHINKUNTI ,  Julie Irene Marcelle BERNAUER ,  Nikolaos TERZENIDIS

IPC: H04L41/0896 ,  H04L41/12

CPC classification number: H04L41/0896 ,  H04L41/12

Abstract: Systems, computer program products, and methods are described herein for dynamic reconfiguration of network communications. An example system includes a first network pod including a first set of network ports, a second network pod including a second set of network ports, a set of network cores, and a first intermediate network switch. The first intermediate switch operatively couples the first network pod, the second network pod, and the set of network cores. The first intermediate network switch is configured to selectively establish full bisectional bandwidth data communication between a subset of the set of network cores, a subset of the first set of network ports, and a subset of the second set of network ports.

公开(公告)号：US20240111702A1

公开(公告)日：2024-04-04

申请号：US17958111

申请日：2022-09-30

Applicant: Mellanox Technologies, Ltd.

Inventor： Rui Xu ,  Mark Rosenbluth ,  Diane Orf ,  Michael Cotsford ,  Shreya Tekade

IPC: G06F13/40 ,  G06F13/24

CPC classification number: G06F13/4045 ,  G06F13/24

Abstract: A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.

公开(公告)号：US11940933B2

公开(公告)日：2024-03-26

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1045 ,  G06F13/38 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F13/1668 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/387 ,  G06F13/4221 ,  G06F15/17331 ,  G06F2009/45579

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US11940660B2

公开(公告)日：2024-03-26

申请号：US18105950

申请日：2023-02-06

Applicant: Mellanox Technologies, Ltd.

Inventor： Andrey Ger ,  Rony Setter ,  Yaniv Kazav

IPC: G02B6/42 ,  G02B6/38 ,  G02B6/40

CPC classification number: G02B6/426 ,  G02B6/3853 ,  G02B6/3881 ,  G02B6/3893 ,  G02B6/406 ,  G02B6/4269 ,  G02B6/4262

Abstract: An OSFP optical transceiver having split multiple fiber optical port using reduced amount of MPO terminations is provided that includes two adjacent sockets integrated into the optical port of the OSFP optical transceiver. The two adjacent sockets are vertically oriented with respect to the mounting baseplate of the OSFP optical transceiver, and each of the two adjacent sockets is adapted to receive an MPO receptacle that terminates the proximal end of a bundle of fibers. The OSFP optical transceiver also includes an optical connection between each socket and a corresponding lens in the OSFP optical transceiver, for transmitting optical signals received from other transceivers into the OSFP optical transceiver and optical signals generated in the OSFP optical transceiver to other transceivers.

公开(公告)号：US20240098104A1

公开(公告)日：2024-03-21

申请号：US17956208

申请日：2022-09-29

Applicant: Mellanox Technologies, Ltd.

Inventor： Ioannis (Giannis) PATRONAS ,  Tamar Viclizki COHEN ,  Vadim GECHMAN ,  Dimitrios SYRIVELIS ,  Paraskevas BAKOPOULOS ,  Nikolaos ARGYRIS ,  Elad MENTOVICH

IPC: H04L9/40 ,  H04L41/16 ,  H04L47/17

CPC classification number: H04L63/1425 ,  H04L41/16 ,  H04L47/17

Abstract: Systems, computer program products, and methods are described herein for machine learning (ML) based network resilience and steering. An example system monitors data traffic across one or more network ports and determines a first data traffic pattern from the data traffic. The system further determines, via a ML subsystem, that the first data traffic pattern is indicative of a security threat to a first network port. In response to determining that the first data traffic pattern is indicative of the security threat to the first network port, the system further isolates the first network port from the one or more network ports.

公开(公告)号：US11934658B2

公开(公告)日：2024-03-19

申请号：US17527197

申请日：2021-11-16

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Boris Pismenny ,  Oren Duer ,  Dror Goldenberg

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0647 ,  G06F3/0659 ,  G06F3/067

Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is to communicate with one or more hosts over a peripheral bus.
The processing circuitry is to expose on the peripheral bus a peripheral-bus device that communicates with the one or more hosts using one or more instances of at least one bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the one or more hosts, and to complete the I/O transactions for the one or more hosts in accordance with one or more instances of at least one network storage protocol, by running at least part of a host-side protocol stack of the at least one network storage protocol.

公开(公告)号：US20240080256A1

公开(公告)日：2024-03-07

申请号：US17901671

申请日：2022-09-01

Applicant: Mellanox Technologies, Ltd.

Inventor： Yamin Friedman ,  Idan Borshteen ,  Roee Moyal ,  Yuval Shpigelman

IPC: H04L45/12 ,  H04L43/0864 ,  H04L45/24 ,  H04L47/52

CPC classification number: H04L45/124 ,  H04L43/0864 ,  H04L45/24 ,  H04L47/52

Abstract: Technologies for spreading a single transport flow across multiple network paths in remote direct memory access (RDMA) over converged Ethernet (RoCE) and InfiniBand are described. A network interface controller receives a first packet and a second packet of a transport flow directed to a second node. The network interface controller assigns a first network routing identifier to the first packet and a second network routing identifier to the second packet, the first network routing identifier corresponding to a first network path between the first and second nodes, the second network routing identifier corresponding to a second network path between the first node and the second node. The network interface controller schedules a first packet of the transport flow to be sent via the first network path and a second packet of the transport flow to be sent via the second network path.

公开(公告)号：US20240073058A1

公开(公告)日：2024-02-29

申请号：US17893692

申请日：2022-08-23

Applicant: Mellanox Technologies Ltd.

Inventor： Amit Kazimirsky ,  Nir Sucher

IPC: H04L12/40 ,  H04L12/10 ,  H04L43/08

CPC classification number: H04L12/40039 ,  H04L12/10 ,  H04L43/08

Abstract: Methods, systems, and machine-readable mediums to predict signal conductor traffic and to transition between signal conductor states in accordance with the predictions. In at least one embodiment, a scoring system is used to select a prediction method, which is used to determine when to transition a signal conductor between active and inactive states.

公开(公告)号：US11909762B2

公开(公告)日：2024-02-20

申请号：US17398708

申请日：2021-08-10

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Andrei Vesnovaty ,  Alexander Vesker ,  Mohammad Sammar

IPC: H04L9/40 ,  H04L69/326 ,  H04L7/00

CPC classification number: H04L63/1458 ,  H04L7/0008 ,  H04L69/326

Abstract: A system for efficiently thwarting syn flood DDoS attacks on a target server including a CPU, the system comprising: network controller hardware having steering capability; and a software application to create and to configure initial steering object/s which define a steering configuration of the network controller and monitor at least one opened connection to the server, including updating the steering configuration responsive to establishment of at least one connection to the server, wherein the network controller hardware's steering capability is used to provide a SYN cookie value used for said thwarting, and to send at least one packet, modified, to the packet's source.

公开(公告)号：US20240056059A1

公开(公告)日：2024-02-15

申请号：US17884878

申请日：2022-08-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Igal Kushnir ,  Naor Peretz ,  Roi Levi

IPC: H03K3/017 ,  H03K19/17784 ,  H03K19/0185 ,  H04L25/03

CPC classification number: H03K3/017 ,  H03K19/17784 ,  H03K19/018521 ,  H04L25/03878

Abstract: Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.