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    Prevention of Ta2O5 mim cap shorting in the beol anneal cycles
    61.
    发明授权
    Prevention of Ta2O5 mim cap shorting in the beol anneal cycles 有权
    在bool退火循环中预防Ta2O5 mim cap短路

    公开(公告)号：US06940117B2

    公开(公告)日：2005-09-06

    申请号：US10249550

    申请日：2003-04-17

    Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Joseph F. Shepard, Jr. ,  Kenneth J. Stein ,  Kunal Vaed

    Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Joseph F. Shepard, Jr. ,  Kenneth J. Stein ,  Kunal Vaed

    IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: H01L28/40 ,  H01L21/31604 ,  H01L28/55

    Abstract: The present invention provides a high-performance metal-insulator-metal (MIM) capacitor which contains a high-k dielectric, yet no substantial shorting of the MIM capacitor is observed. Specifically, shorting of the MIM capacitor is substantially prevented in the present invention by forming a passivation layer between the high-k dielectric layer and each of the capacitor's electrodes. The inventive MIM capacitor includes a first conductor; a first passivation layer located atop the first conductor; a high-k dielectric layer located atop the first passivation layer; a second passivation layer located atop the high k dielectric layer; and a second conductor located atop the second passivation layer.

    Abstract translation: 本发明提供了一种高性能金属绝缘体金属（MIM）电容器，其包含高k电介质，但没有观察到MIM电容器的实质短路。 具体地说，在本发明中，通过在高k电介质层和电容器的电极之间形成钝化层，基本上防止了MIM电容器的短路。 本发明的MIM电容器包括第一导体; 位于第一导体顶部的第一钝化层; 位于第一钝化层顶部的高k电介质层; 位于高k电介质层顶部的第二钝化层; 以及位于第二钝化层顶部的第二导体。

    C implants for improved SiGe bipolar yield
    62.
    发明授权
    C implants for improved SiGe bipolar yield 有权
    C植入物用于改善SiGe双极产率

    公开(公告)号：US06720590B2

    公开(公告)日：2004-04-13

    申请号：US10338476

    申请日：2003-01-08

    Applicant: Douglas D. Coolbaugh ,  Kathryn T. Schonenberg

    Inventor： Douglas D. Coolbaugh ,  Kathryn T. Schonenberg

    IPC: H01L310328

    CPC classification number: H01L29/7378 ,  H01L21/26506 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/66242 ,  H01L29/66318

    Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

    Abstract translation: 提供了一种改善SiGe双极性产率以及制造SiGe异质结双极晶体管的方法。 本发明的方法包括将碳C离子注入到器件的以下区域之一：集电极区域，子集电极区域，非本征基极区域和集电极 - 基极结区域。 在优选实施例中，上述每个区域包括C植入物。

    Stackable programmable passive device and a testing method
    64.
    发明授权
    Stackable programmable passive device and a testing method 有权
    可堆叠可编程无源器件和测试方法

    公开(公告)号：US08294505B2

    公开(公告)日：2012-10-23

    申请号：US11161932

    申请日：2005-08-23

    Applicant: Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

    Inventor： Fen Chen ,  Douglas D. Coolbaugh ,  Baozhen Li

    IPC: G06G7/19 ,  H01L29/00

    CPC classification number: H01L27/101 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.

    Abstract translation: 一种包括第一节点和第二节点的可编程无源设备。 电耦合到第一节点的多个无源器件元件。 多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。

    MIM capacitor structure in FEOL and related method
    65.
    发明授权
    MIM capacitor structure in FEOL and related method 有权
    FEOL中的MIM电容器结构及相关方法

    公开(公告)号：US08125049B2

    公开(公告)日：2012-02-28

    申请号：US12618830

    申请日：2009-11-16

    Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

    Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

    IPC: H01L27/06 ,  H01L27/07

    CPC classification number: H01L27/0629 ,  H01L28/60

    Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

    Abstract translation: 电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器 由第二电容器板，电容器电介质层和半导体衬底形成。

    MIM CAPACITOR STRUCTURE IN FEOL AND RELATED METHOD
    67.
    发明申请
    MIM CAPACITOR STRUCTURE IN FEOL AND RELATED METHOD 有权
    MIM电容器结构及相关方法

    公开(公告)号：US20110115005A1

    公开(公告)日：2011-05-19

    申请号：US12618830

    申请日：2009-11-16

    Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

    Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Robert M. Rassel ,  Anthony K. Stamper

    IPC: H01L27/06 ,  H01L21/02

    CPC classification number: H01L27/0629 ,  H01L28/60

    Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

    Abstract translation: 电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器 由第二电容器板，电容器电介质层和半导体衬底形成。

    Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme
    69.
    发明授权
    Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme 失效
    制造更高性能的电容密度MIMcap的廉价方法可以集成到铜互连方案中

    公开(公告)号：US07687867B2

    公开(公告)日：2010-03-30

    申请号：US11846248

    申请日：2007-08-28

    Applicant: Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  William J. Murphy ,  Vidhya Ramachandran

    Inventor： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  William J. Murphy ,  Vidhya Ramachandran

    IPC: H01L29/72

    CPC classification number: H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode. The bottom and top plate electrodes can comprise the same or different conductive metal.

    Abstract translation: 提供了一种将MIM电容器集成到导电互连级别中的方法，具有低成本影响，并且提供了比现有集成方法高的产量，可靠性和性能。 这通过将用于MIM电容器电平对准的先前级别的电介质凹入，然后MIM电容器膜的沉积和图案化来实现。 具体地，该方法包括提供包括布线层的衬底，所述布线层包括形成在电介质层中的至少一个导电布线; 选择性地去除所述电介质层的一部分以使所述电介质层在所述至少一个导电互连的上表面下方凹陷; 在所述至少一个导电互连和所述凹入的介电层上形成电介质叠层; 以及在介电叠层上形成金属绝缘体金属（MIM）电容器。 MIM电容器包括底板电极，电介质和顶板电极。 底板和顶板电极可以包括相同或不同的导电金属。

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