公开(公告)号：US09823889B2

公开(公告)日：2017-11-21

申请号：US14648713

申请日：2013-01-08

Applicant: Freescale Semiconductor, Inc.

Inventor： Robert Krutsch ,  Laurent Emmerich

IPC: G06T15/20 ,  G06F3/14 ,  G06F3/147 ,  B60K37/02 ,  G06T15/00

CPC classification number: G06F3/1431 ,  B60K37/02 ,  G06F3/147 ,  G06T15/005 ,  G06T15/20 ,  G06T2215/16

Abstract: A method of estimating a fragment count for the display of at least one three-dimensional (3D) object. The method comprises determining an ellipsoid representative of a set of vertices defined by coordinates of the at least one 3D object, applying a transformation to the ellipsoid, calculating a projection area of the transformed ellipsoid, and estimating the fragment count for the display of the 3D object based at least partly on the calculated projection area of the transformed ellipsoid.

公开(公告)号：US09818863B2

公开(公告)日：2017-11-14

申请号：US14990765

申请日：2016-01-07

Applicant: Freescale Semiconductor, Inc.

Inventor： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/225 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/2253 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path.

公开(公告)号：US20170322891A1

公开(公告)日：2017-11-09

申请号：US15298086

申请日：2016-10-19

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Bin Feng ,  Shuwei Wu ,  Shixiong Lu

IPC: G06F12/14 ,  G06F21/62

CPC classification number: G06F12/1491 ,  G06F12/1475 ,  G06F21/62 ,  G06F21/6218 ,  G06F2212/1052

Abstract: A device for secure data storage has a host unit that obtains data stored on an external device at an external storage address; a user signal generator that generates a user defined security signal based on the external storage address of the data that indicates a security level of the data; a storage address determining unit that determines an internal storage address for the data based on the security level of the data; and a storage unit that stores the data at the internal storage address corresponding to the security level.

公开(公告)号：US20170322098A1

公开(公告)日：2017-11-09

申请号：US15144985

申请日：2016-05-03

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Chad Dawson ,  Keith Kraver ,  Shiraz Contractor

IPC: G01L9/00 ,  G01L27/00

CPC classification number: G01L9/0072 ,  G01L27/007

Abstract: A pressure sensor device and a method for testing the pressure sensor device is provided. The pressure sensor device includes a first pressure sensor cell having a first capacitance value, and a second pressure sensor cell having a second capacitance value, the second capacitance value being different from the first capacitance value. In one embodiment, the method includes determining a temperature coefficient offset to test for faults in the pressure sensor device. In another embodiment, the method includes determining a differential mode calculation and a common mode calculation. A fault exists if the differential and common mode calculations do not agree.

公开(公告)号：US09810843B2

公开(公告)日：2017-11-07

申请号：US13914178

申请日：2013-06-10

Applicant: Freescale Semiconductor, Inc.

Inventor： Tab A. Stephens ,  Perry H. Pelley ,  Michael B. McShane

IPC: G02B6/12 ,  G02B6/136 ,  G02B6/13 ,  G02B6/125 ,  G02B6/43 ,  G02B6/42

CPC classification number: G02B6/136 ,  G02B6/125 ,  G02B6/131 ,  G02B6/4214 ,  G02B6/43 ,  G02B2006/12061 ,  G02B2006/12104

Abstract: An integrated circuit optical backplane die and associated semiconductor fabrication process are described for forming optical backplane mirror structures for perpendicularly deflecting optical signals out of the plane of the optical backplane die by selectively etching an optical waveguide semiconductor layer (103) on an optical backplane die wafer using an orientation-dependent anisotropic wet etch process to form a first recess opening (107) with angled semiconductor sidewall surfaces (106) on the optical waveguide semiconductor layer, where the angled semiconductor sidewall surfaces (106) are processed to form an optical backplane mirror (116) for perpendicularly deflecting optical signals to and from a lateral plane of the optical waveguide semiconductor layer.

公开(公告)号：US09799617B1

公开(公告)日：2017-10-24

申请号：US15221372

申请日：2016-07-27

Applicant: FREESCALE SEMICONDUCTOR INC.

Inventor： Mitchell Curiel ,  Huan Gim Chan ,  Wan Foong Kho

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/48 ,  H01L24/89 ,  H01L24/98 ,  H01L2224/033

Abstract: Methods for repacking copper wire bonded microelectronic die (that is, die having bond pads bonded to copper wire bonds) are provided. In one embodiment, the repackaging method includes the step or process of obtaining a microelectronic package containing copper wire bonds and a microelectronic die, which includes bond pads to which the copper wire bonds are bonded. The microelectronic die is extracted from the microelectronic package in a manner separating the copper wire bonds from the bond pads. The microelectronic die is then attached or mounted to a Failure Analysis (FA) package having electrical contact points thereon. Electrical connections are then formed between the bond pads of the microelectronic die and the electrical contact points of the FA package at least in part by printing an electrically-conductive material onto the bond pads.

公开(公告)号：US09797921B2

公开(公告)日：2017-10-24

申请号：US14844965

申请日：2015-09-03

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Tehmoor M. Dar ,  Bruno J. Debeurre ,  Raimondo P. Sessego

IPC: G01P21/00 ,  G01P15/125

CPC classification number: G01P21/00

Abstract: A system includes a MEMS sensor having dual proof masses capable of moving independently from one another in response to forces imposed upon the proof masses. Each proof mass includes an independent set of sense contacts configured to provide output signals corresponding to the physical displacement of the corresponding sense mass. A switch system is in communication with the sense contacts. The switch system is configured to enable a sense mode and various test modes for the MEMS sensor. When the switch system enables a sense mode, output signals from the sense contacts can be combined to produce sense signals. When the switch system enables a test mode, the second contacts are electrically decoupled from one another to disassociate the output signals from one another. The independent sense contacts and switch system enable the concurrent compensation and calibration of the proof masses along two different sense axes.

公开(公告)号：US20170294994A1

公开(公告)日：2017-10-12

申请号：US15092338

申请日：2016-04-06

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： ROI MENAHEM SHOR ,  AVI GAL ,  AVRAHAM HORN

IPC: H04L5/00 ,  H04W72/08 ,  H04L27/26 ,  H04W72/04

CPC classification number: H04L5/0007 ,  H04L27/2607 ,  H04W72/044 ,  H04W72/087 ,  H04W88/085

Abstract: The present application relates to a Common Public Radio Interface, CPRI, lane controller and a method of operating thereof. The CPRI lane controller comprises a transaction counter, a symbol counter and a comparator. The transaction counter is provided for maintaining a current aggregated transactions' size, Sizetrans, representative of an accumulated size of DMA transactions performed by a DMA controller in response to symbols transferred on a CPRI link from or to the CPRI lane controller. The symbol counter is provided for maintaining a current aggregated expected symbols' size, Sizeexp, representative of an accumulated size of a sequence of transferred symbols and a currently transferred symbol. The comparator is configured to issue a symbol awareness signal, SAS, in case the current aggregated transactions' size, Sizetrans, exceeds the current aggregated expected symbols' size, Sizeexp.

公开(公告)号：US20170294393A1

公开(公告)日：2017-10-12

申请号：US15093713

申请日：2016-04-07

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： David F. Abdo ,  Sivanesan A/L Sathiapalan

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/03019 ,  H01L2224/0312 ,  H01L2224/03462 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05601 ,  H01L2224/05611 ,  H01L2224/2746 ,  H01L2224/27825 ,  H01L2224/29 ,  H01L2224/29007 ,  H01L2224/29023 ,  H01L2224/29036 ,  H01L2224/29144 ,  H01L2224/29562 ,  H01L2224/2957 ,  H01L2224/29644 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/80048 ,  H01L2224/80355 ,  H01L2224/80359 ,  H01L2224/83048 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83355 ,  H01L2924/01079 ,  H01L2924/1033 ,  H01L2924/0105 ,  H01L2924/00014

Abstract: A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

公开(公告)号：US20170293375A1

公开(公告)日：2017-10-12

申请号：US15094333

申请日：2016-04-08

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： PETR CHOLASTA

IPC: G06F3/044 ,  G06F3/041

CPC classification number: G06F3/044 ,  G06F3/0416 ,  H03K17/962 ,  H03K2217/960705

Abstract: A capacitive sensor system includes a capacitive sensor device having a sense electrode that includes a first capacitor, a first supply voltage in , a first switch operable to couple the sense electrode to the first supply voltage during a first mode and an analog to digital converter during a second mode, a second switch operable to couple a second capacitor to a second supply voltage during the first mode and to an open circuit during the second mode, and a resistive element that includes a first terminal coupled between the first capacitor and the first switch, and a second terminal coupled between the second capacitor and the second switch.