公开(公告)号：US09541521B1

公开(公告)日：2017-01-10

申请号：US14928877

申请日：2015-10-30

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Md M. Hoque ,  Weize Chen ,  Patrice M. Parris

IPC: G01N27/414 ,  G01N27/333

CPC classification number: G01N27/4148 ,  G01N27/4145

Abstract: A mechanism is provided for enhancing the sensitivity of an ion-sensitive semiconductor device by creating a second gate coupled to a sense plate that can improve the amount of charge brought to the ion-sensitive semiconductor device conductivity modulated region (e.g., a channel region of an ISFET). This is accomplished by utilizing a buried dielectric layer associated with the ion-sensitive semiconductor device conductivity modulated region as the second gate dielectric. The buried dielectric layer is coupled to the sense plate using an isolated well region as a conductor that is coupled to metal layers extending to the sense plate. Some embodiments further use the buried dielectric layer as the sole gate dielectric for the semiconductor device, thereby allowing the traditional gate dielectric region to be coupled to a protection diode. This protection diode then protects the gate dielectric from plasma induced damage and electrostatic discharge.

Abstract translation: 提供了一种用于通过产生耦合到感测板的第二栅极来提高离子敏感半导体器件的灵敏度的机制，其可以改善引入到离子敏感半导体器件导电性调制区域的电荷量（例如， 一个ISFET）。 这是通过利用与离子敏感半导体器件导电性调制区域相关联的掩埋介电层作为第二栅极电介质来实现的。 埋置的介电层使用隔离的阱区域作为导体耦合到感测板，该导体耦合到延伸到感测板的金属层。 一些实施例进一步使用掩埋介质层作为用于半导体器件的唯一栅极电介质，从而允许传统的栅介质区域耦合到保护二极管。 该保护二极管然后保护栅极电介质不受等离子体引起的损伤和静电放电。

公开(公告)号：US09466608B1

公开(公告)日：2016-10-11

申请号：US14925933

申请日：2015-10-28

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Weize Chen ,  Richard J De Souza ,  Patrice M Parris

IPC: H01L21/336 ,  H01L27/115 ,  H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/28035 ,  H01L21/28282 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823828 ,  H01L27/0922 ,  H01L27/11521 ,  H01L27/11543 ,  H01L29/42332 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for making a semiconductor structure includes forming an oxide layer onto non-volatile memory, high, and low voltage device regions of a substrate and forming a first gate material layer over the oxide layer. The first gate material layer is patterned to form a set of memory device select gates in the non-volatile memory device region and a set of gates in the high voltage device region. The patterning is performed while maintaining the oxide and first gate material layers over the low voltage device region. The method also includes forming a second gate material layer over the structure and forming a non-volatile storage layer between the set of select gates and the second gate material layer, from which a set of memory device control gates is patterned. Thereafter, the first gate material layer is patterned to form a set of gates in the low voltage device region.

Abstract translation: 制造半导体结构的方法包括在衬底的非易失性存储器，高电压和低电压器件区域上形成氧化物层，并在氧化物层上形成第一栅极材料层。 图案化第一栅极材料层以在非易失性存储器件区域中形成一组存储器件选择栅极，并在高电压器件区域中形成一组栅极。 在将氧化物和第一栅极材料层保持在低电压器件区域上的同时进行图案化。 该方法还包括在该结构上形成第二栅极材料层，并在该组选择栅极和第二栅极材料层之间形成非易失性存储层，一组存储器件控制栅极从该栅极材料层构图。 此后，第一栅极材料层被图案化以在低电压器件区域中形成一组栅极。

公开(公告)号：US20160118495A1

公开(公告)日：2016-04-28

申请号：US14990765

申请日：2016-01-07

Applicant: Freescale Semiconductor, Inc.

Inventor： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC: H01L29/78 ,  H01L21/225 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/2253 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Abstract translation: 一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极 区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。 身体区域和器件隔离区域中的至少一个包括沿着有源区域的横向周边设置的多个外围构成区域，每个周边的构成区域在器件隔离区域和体区域之间限定非均匀的间隔 。 在多个周边组成区域的相应周边区域处的不均匀间隔在导通路径中建立低于第二击穿电压的第一击穿电压。

公开(公告)号：US10026820B2

公开(公告)日：2018-07-17

申请号：US15078860

申请日：2016-03-23

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Weize Chen ,  Cheong Min Hong ,  Konstantin V. Loiko ,  Jane A. Yater

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/11568 ,  H01L21/8234

Abstract: A method of forming a semiconductor device using a substrate includes forming a first select gate over the substrate, a charge storage layer over the first select gate, over the second select gate, and over the substrate in a region between the first select gate and the second select gate, wherein the charge storage layer is conformal, and a control gate layer over the charge storage layer, wherein the control gate layer is conformal. The method further includes performing a first implant that penetrates through the control gate layer in a middle portion of the region between the first select gate and the second select gate to the substrate to form a doped region in the substrate in a first portion of the region between the first select gate and the second select gate that does not reach the first select gate and does not reach the second select gate.

公开(公告)号：US09570440B2

公开(公告)日：2017-02-14

申请号：US14859806

申请日：2015-09-21

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC: H01L27/07 ,  H01L29/66 ,  H01L21/761

CPC classification number: H01L27/0727 ,  H01L21/761 ,  H01L29/66143 ,  H01L29/66681

Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region of the second conductivity type, and the diode circuit is connected between the isolation structure and the body region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

Abstract translation: 半导体器件和驱动电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底区域内的有源器件和二极管电路。 掩埋层位于顶部衬底表面下方，并且具有第二导电类型。 沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。 有源器件包括第二导电类型的体区，并且二极管电路连接在隔离结构和体区之间。 二极管电路可以包括一个或多个肖特基二极管和/或PN结二极管。 在另外的实施例中，二极管电路可以包括与肖特基和/或PN二极管串联和/或并联的一个或多个电阻网络。

公开(公告)号：US09818863B2

公开(公告)日：2017-11-14

申请号：US14990765

申请日：2016-01-07

Applicant: Freescale Semiconductor, Inc.

Inventor： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/225 ,  H01L29/08

CPC classification number: H01L29/7823 ,  H01L21/2253 ,  H01L29/0626 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path.

公开(公告)号：US09607981B2

公开(公告)日：2017-03-28

申请号：US14827909

申请日：2015-08-17

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC: H01L27/06 ,  H01L29/10 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/04 ,  H01L29/16 ,  H01L29/861 ,  H01L29/872 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0629 ,  H01L27/0288 ,  H01L29/04 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66681 ,  H01L29/7818 ,  H01L29/782 ,  H01L29/861 ,  H01L29/872

Abstract: Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

公开(公告)号：US09502304B2

公开(公告)日：2016-11-22

申请号：US14846115

申请日：2015-09-04

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Weize Chen ,  Hubert M. Bode ,  Richard J. De Souza ,  Patrice M. Parris

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L21/761 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H03K17/687 ,  H03K17/74

CPC classification number: H01L21/823481 ,  H01L21/761 ,  H01L21/823418 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7835 ,  H03K17/6871 ,  H03K17/74 ,  H03K2217/0018 ,  H03K2217/0036

Abstract: Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a drain region of the second conductivity type, and the diode circuit is connected between the isolation structure and the drain region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

公开(公告)号：US09397230B2

公开(公告)日：2016-07-19

申请号：US14810140

申请日：2015-07-27

Applicant: FREESCALE SEMICONDUCTOR INC.

Inventor： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC: H01L31/107 ,  H01L29/866 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/866 ,  H01L21/76224 ,  H01L29/0611 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/66106

Abstract: Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.