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79 条记录 (耗时 0.028 秒)

    Transmitter, receiver, and radio communications system and method
    62.
    发明申请
    Transmitter, receiver, and radio communications system and method 失效
    发射机，接收机和无线电通信系统和方法

    公开(公告)号：US20020102951A1

    公开(公告)日：2002-08-01

    申请号：US10011763

    申请日：2001-12-11

    申请人： FUJITSU QUANTUM DEVICES LIMITED

    发明人： Hiroshi Nakano ,  Yasutake Hirachi

    IPC分类号： H04B001/04

    CPC分类号： H03D7/00

    摘要： Transmitter and receiver for wireless communications with improved accuracy and stability in radio frequency control. A transmitter mixes an information-carrying signal (first signal) and a non-modulated wave signal (second signal) with a carrier signal, thereby producing a first and second radio frequency signals for radio wave transmission. A receiver mixes those two radio frequency signals to extract the original information signal. While the received radio frequency signals contain some frequency fluctuations and phase noises that have been introduced at the sending end, such unstable components nullf will cancel out at the receiving end.

    摘要翻译： 用于无线通信的发射机和接收机，具有改进的射频控制的精度和稳定性。 发射机将信息携带信号（第一信号）和非调制波信号（第二信号）与载波信号进行混合，从而产生用于无线电波传输的第一和第二射频信号。 接收机将这两个射频信号混合以提取原始信息信号。 虽然接收到的射频信号包含在发送端引入的一些频率波动和相位噪声，但这种不稳定的组件DELTAf将在接收端抵消。

    Clock signal correction circuit and semiconductor device implementing the same
    63.
    发明申请
    Clock signal correction circuit and semiconductor device implementing the same 失效
    时钟信号校正电路和实现相同的半导体器件

    公开(公告)号：US20020097075A1

    公开(公告)日：2002-07-25

    申请号：US10046186

    申请日：2002-01-16

    申请人： Fujitsu Quantum Devices Limited.

    发明人： Masaaki Ono ,  Masataka Kazuno ,  Narito Matsuno

    IPC分类号： H03K003/017

    CPC分类号： H03K5/1534 ,  H03K5/133 ,  H03K5/1565 ,  H03K5/159

    摘要： A clock signal correction circuit which corrects duty cycle distortions of a clock signal in a simple and accurate way. A frequency divider divides the frequency of a given input clock signal by a natural number n, thereby producing a divided clock signal. The phase of this divided clock signal is identified by a phase detector. By adding an appropriate delay to the divided clock signal according to the identified signal phase, a delay unit produces a delayed divided clock signal. A logical operator creates an output clock signal by performing a logical operation on the original divided clock signal and the delayed divided clock signal.

    摘要翻译： 时钟信号校正电路，以简单准确的方式校正时钟信号的占空比失真。 分频器将给定输入时钟信号的频率除以自然数n，从而产生分频时钟信号。 该分频时钟信号的相位由相位检测器识别。 通过根据所识别的信号相位向分配的时钟信号添加适当的延迟，延迟单元产生延迟的分频时钟信号。 逻辑运算符通过对原始分频时钟信号和延迟分频时钟信号执行逻辑运算来创建输出时钟信号。

    Buffer circuit comprising load, follower transistor and current source connected in series
    65.
    发明申请
    Buffer circuit comprising load, follower transistor and current source connected in series 失效
    缓冲电路包括串联连接的负载，跟随晶体管和电流源

    公开(公告)号：US20010052819A1

    公开(公告)日：2001-12-20

    申请号：US09871641

    申请日：2001-06-04

    申请人： FUJITSU QUANTUM DEVICES LIMITED

    发明人： Miki Kubota

    IPC分类号： H03F003/16

    CPC分类号： H03F3/45183 ,  H03F3/505 ,  H03F2203/45571 ,  H03F2203/45608 ,  H03F2203/45612 ,  H03F2203/45702

    摘要： An input buffer circuit 11X is a source follower circuit and comprises a load 114 and enhancement FETs 111 and 112A connected in series between power supply lines VDD and VSS. A DC bias VB1 is applied to the gate of the FET 112A to act it as a current source, and an AC current component of the drain potential VD of the FET 111 is provided through a capacitor 113 to the gate of the FET 112A. If an inductor as an matching circuit is connected in series to the capacitor 113, a band pass filter is constructed, and the gain of the circuit 11X becomes especially high at the resonance frequency thereof. At high frequencies, the interconnection coupled to the capacitor 113 has a parasitic inductance, and the output waveform of the circuit 11X has a high frequency noise. In this case, a damping transistor is connected between the capacitor 113 and the gate of the FET 112A to obtain a flat gain by adjusting the gate potential thereof.

    摘要翻译： 输入缓冲器电路11X是源极跟随器电路，并且包括串联连接在电源线VDD和VSS之间的负载114和增强FET 111和112A。 将DC偏压VB1施加到FET 112A的栅极以用作电流源，并且通过电容器113将FET 111的漏极电位VD的AC电流分量提供给FET 112A的栅极。 如果作为匹配电路的电感器串联连接到电容器113，则构造带通滤波器，并且电路11X的增益在其谐振频率处变得特别高。 在高频下，耦合到电容器113的互连件具有寄生电感，并且电路11X的输出波形具有高频噪声。 在这种情况下，阻尼晶体管连接在电容器113和FET 112A的栅极之间，通过调节其栅极电位而获得平坦的增益。

    Semiconductor photodetection device and fabrication process thereof
    66.
    发明申请
    Semiconductor photodetection device and fabrication process thereof 失效
    半导体光电检测装置及其制造方法

    公开(公告)号：US20010048118A1

    公开(公告)日：2001-12-06

    申请号：US09873264

    申请日：2001-06-05

    申请人： Fujitsu Quantum Devices Limited

    发明人： Toru Uchida ,  Chikashi Anayama

    IPC分类号： H01L021/00 ,  H01L031/0328

    CPC分类号： B82Y20/00 ,  H01L31/03046 ,  H01L31/035263 ,  H01L31/105 ,  Y02E10/544

    摘要： A semiconductor photodetection device includes a photodetection layer formed of an alternate and repetitive stacking of an optical absorption layer accumulating therein a compressive strain and a stress-compensating layer accumulating therein a compensating tensile strain, wherein the optical absorption layer has a thickness larger than a thickness of the stress-compensating layer.

    摘要翻译： 半导体光电检测装置包括由在其中蓄积压缩应变的光吸收层和在其中累积补偿拉伸应变的应力补偿层的交替重复堆叠形成的光电检测层，其中光吸收层的厚度大于厚度 的应力补偿层。

    Microwave voltage controlled oscillator
    68.
    发明申请
    Microwave voltage controlled oscillator 有权
    微波压控振荡器

    公开(公告)号：US20010026195A1

    公开(公告)日：2001-10-04

    申请号：US09814753

    申请日：2001-03-23

    申请人： FUJITSU QUANTUM DEVICES LIMITED

    发明人： Tsuneo Tokumitsu ,  Osamu Baba

    IPC分类号： H03B005/18

    CPC分类号： H03B5/1847

    摘要： A negative resistance circuit having an output terminal is connected to a first terminal of a strip shaped resonator. Anode of a variable capacitance diode is connected to a second terminal of the strip shaped resonator via a capacitor 1null. Cathode of the variable capacitance diode is grounded. One terminal of a high impedance strip shaped line is connected to the anode of the variable capacitance diode. Other terminal of the strip shaped line is grounded via a capacitor 4. The capacitor 4 has sufficiently low impedance at an oscillation frequency.

    摘要翻译： 具有输出端子的负电阻电路连接到带状谐振器的第一端子。 可变电容二极管的阳极通过电容器1'连接到带状谐振器的第二端子。 可变电容二极管的阴极接地。 高阻抗条状线的一个端子连接到可变电容二极管的阳极。 带状线的其他端子通过电容器4接地。电容器4在振荡频率下具有足够低的阻抗。

    Microwave monolithic integrated circuit and fabrication process thereof
    69.
    发明申请
    Microwave monolithic integrated circuit and fabrication process thereof 失效
    微波单片集成电路及其制造工艺

    公开(公告)号：US20010012652A1

    公开(公告)日：2001-08-09

    申请号：US09776722

    申请日：2001-02-06

    申请人： FUJITSU QUANTUM DEVICES LIMITED

    发明人： Hajime Matsuda

    IPC分类号： H01L021/338

    CPC分类号： H01L29/66871 ,  H01L21/28575 ,  H01L21/28587 ,  H01L21/8252

    摘要： A microwave monolithic integrated circuit comprises a T-shaped gate electrode including a Schottky gate electrode formed on a first region of a compound semiconductor substrate, a pair of ohmic electrodes making an ohmic contact with a surface of the substrate in the first region at respective sides of the T-shaped gate electrode, a lower capacitor electrode pattern formed on a second region of the compound semiconductor substrate with a composition substantially identical with a low-resistance, top electrode constituting the T-shaped gate electrode on the Schottky gate electrode, a dielectric film formed on the lower electrode pattern, and an upper electrode pattern formed on the dielectric film.

    摘要翻译： 微波单片集成电路包括：T形栅电极，其包括形成在化合物半导体衬底的第一区域上的肖特基栅极电极，在相应侧的第一区域中与衬底的表面欧姆接触的一对欧姆电极 形成在化合物半导体基板的第二区域上的下电容器电极图案，其组成与构成肖特基栅电极上的T形栅电极的低电阻顶电极的组成基本相同， 形成在下电极图案上的电介质膜和形成在电介质膜上的上电极图案。

    Semiconductor light-receiving device
    70.
    发明申请
    Semiconductor light-receiving device 失效
    半导体光接收装置

    公开(公告)号：US20040056250A1

    公开(公告)日：2004-03-25

    申请号：US10665204

    申请日：2003-09-22

    申请人： FUJITSU QUANTUM DEVICES LIMITED

    发明人： Gang Wang ,  Yoshihiro Yoneda

    IPC分类号： H01L029/04 ,  H01L031/036 ,  H01L031/0376 ,  H01L031/20

    CPC分类号： H01L31/105 ,  H01L31/1844 ,  Y02E10/544

    摘要： A semiconductor light-receiving device includes: a semi-insulating substrate; a semiconductor layer of a first conduction type that is formed on the semi-insulating substrate; a buffer layer of the first conduction type that is formed on the semi-insulating substrate and has a lower impurity concentration than the semiconductor layer of the first conduction type; a light absorption layer that is formed on the buffer layer and generates carriers in accordance with incident light; a semiconductor layer of a second conduction type that is formed on the light absorption layer; and a semiconductor intermediate layer that is interposed between the buffer layer and the light absorption layer, and has a forbidden bandwidth within a range lying between the forbidden bandwidth of the buffer layer and the forbidden bandwidth of the light absorption layer.

    摘要翻译： 半导体光接收装置包括：半绝缘基板; 形成在半绝缘基板上的第一导电型半导体层; 所述第一导电类型的缓冲层形成在所述半绝缘基板上并且具有比所述第一导电类型的半导体层更低的杂质浓度; 形成在缓冲层上并根据入射光产生载流子的光吸收层; 形成在所述光吸收层上的第二导电类型的半导体层; 以及介于缓冲层和光吸收层之间的半导体中间层，并且在缓冲层的禁止带宽和光吸收层的禁止带宽之间的范围内具有禁止带宽。