公开(公告)号：US10734233B2

公开(公告)日：2020-08-04

申请号：US15902098

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Keith Tabakman

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

公开(公告)号：US20200243645A1

公开(公告)日：2020-07-30

申请号：US16262052

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  George R. Mulfinger ,  Hui Zang ,  Liu Jiang ,  Zhenyu Hu

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.

公开(公告)号：US20200243126A1

公开(公告)日：2020-07-30

申请号：US16261617

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: G11C11/16 ,  G11C13/00

Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.

公开(公告)号：US10727327B2

公开(公告)日：2020-07-28

申请号：US15882053

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rahul Mishra ,  Vibhor Jain ,  Ajay Raman ,  Robert J. Gauthier

IPC: H01L29/749 ,  H01L29/66 ,  H01L29/74 ,  H01L27/02 ,  H01L29/737

Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.

公开(公告)号：US10727251B2

公开(公告)日：2020-07-28

申请号：US16207730

申请日：2018-12-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Dünkel ,  Johannes Müller ,  Lars Müller-Meskamp

IPC: G11C11/22 ,  G11C5/12 ,  H01L21/28 ,  H01L27/1159 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/762 ,  H01L21/3065 ,  G11C11/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to rounded shaped transistors and methods of manufacture. The structure includes a gate structure composed of a metal electrode and a rounded ferroelectric material which overlaps an active area in a width direction into an isolation region.

公开(公告)号：US10726896B1

公开(公告)日：2020-07-28

申请号：US16261617

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

Abstract: A memory structure includes a first memory array with two transistor-two variable resistor memory cells and a second memory array with one transistor-one variable resistor memory cells, which are each selectively operable in read, write and standby modes. The first memory array and the second memory array are interleaved so that, when the second memory operates in the read mode, the first memory array automatically and concurrently operates in a reference mode. A method of operating the memory structure includes, when the second memory array operates in the read mode, automatically and concurrently operating the first memory array in the reference mode so that the first memory array generates and outputs a statistical reference voltage, which is between the low and high voltages of a nominal memory cell within the second memory array and which is employed by the second memory array to sense a stored data value.

公开(公告)号：US20200227424A1

公开(公告)日：2020-07-16

申请号：US16246639

申请日：2019-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xuan Anh Tran ,  Sunil Kumar Singh ,  Shyue Seng Tan

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/78 ,  H01L29/423 ,  H01L21/306 ,  H01L29/66 ,  H01L21/308

Abstract: One illustrative MPT device disclosed herein includes an active region and an inactive region, isolation material positioned between the active region and the inactive region, the isolation material electrically isolating the active region from the inactive region, and an FG MTP cell formed in the active region. In this example, the FG MTP cell includes a floating gate, wherein first, second and third portions of the floating gate are positioned above the active region, the inactive region and the isolation material, respectively, and a control gate positioned above at least a portion of the inactive region, wherein the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate.

公开(公告)号：US20200227350A1

公开(公告)日：2020-07-16

申请号：US16248317

申请日：2019-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jaladhi Mehta ,  Brian Greene ,  Daniel J. Dechene ,  Ahmed Hassan

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/76

Abstract: Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions.

公开(公告)号：US20200227323A1

公开(公告)日：2020-07-16

申请号：US16246536

申请日：2019-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： HUI ZANG ,  RUILONG XIE ,  JESSICA MARY DECHENE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762

Abstract: A method of fabricating a semiconductor device is provided, which includes providing sacrificial gate structures over a plurality of fins, wherein the sacrificial gate structures include a first sacrificial gate structure and a second sacrificial gate structure. A fin cut process is performed to form a fin cut opening in the first sacrificial gate structure. A gate cut process is performed to form a gate cut opening in the second sacrificial gate structure. A first dielectric layer is deposited in the fin cut opening and the gate cut opening, and the first dielectric layer is recessed in the openings. A second dielectric layer is deposited over the first dielectric layer in the fin cut opening and the gate cut opening to concurrently form a diffusion break structure and a gate cut structure respectively.

公开(公告)号：US10707881B1

公开(公告)日：2020-07-07

申请号：US16440179

申请日：2019-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Seydou Ba ,  Ahmed R. Fridi

IPC: H03L7/00 ,  H03L7/08 ,  H03H11/16 ,  H03K5/13 ,  H03L7/093 ,  H03L7/099 ,  H03L7/197

Abstract: The present disclosure relates to a structure including an adaptive noise canceller circuit which is configured to suppress noise in a feedback sigma-delta modulator circuit and provide real-time tracking of a noise cancellation signal.