公开(公告)号：US08975683B2

公开(公告)日：2015-03-10

申请号：US12880891

申请日：2010-09-13

申请人： Ki-Hong Lee ,  Kwon Hong ,  Dae-Gyu Shin

发明人： Ki-Hong Lee ,  Kwon Hong ,  Dae-Gyu Shin

IPC分类号： H01L29/792 ,  H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/8221 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.

摘要翻译： 非易失性存储器件包括具有管道通道孔的管道绝缘层，设置在管道绝缘层上方的管道栅极，一对具有柱状电池沟道的电池串，以及连接柱状电池槽和围绕内侧壁的管道 和管道通孔的底部。

公开(公告)号：US08946808B2

公开(公告)日：2015-02-03

申请号：US13603339

申请日：2012-09-04

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Hyun Soo Shon

IPC分类号： H01L29/792 ,  H01L29/76 ,  H01L29/788 ,  H01L21/4763

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/32133 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

公开(公告)号：US08890251B2

公开(公告)日：2014-11-18

申请号：US13598604

申请日：2012-08-29

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon

IPC分类号： H01L29/40

CPC分类号： H01L27/11582 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L29/4238 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes a substrate, and a gate line, located over the substrate, which includes a first conductive layer and one or more second conductive pattern layers located in the first conductive layer. The second conductive pattern layer comprises a metal layer to thus reduce resistance of a gate line.

摘要翻译： 半导体器件包括位于衬底上方的衬底和栅极线，栅极线包括第一导电层和位于第一导电层中的一个或多个第二导电图案层。 第二导电图案层包括金属层，从而降低栅极线的电阻。

公开(公告)号：US08709894B2

公开(公告)日：2014-04-29

申请号：US13234422

申请日：2011-09-16

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon ,  Jin Ho Bin

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Il Young Kwon ,  Jin Ho Bin

IPC分类号： H01L21/336

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region.

摘要翻译： 公开了一种3D结构的非易失性半导体存储器件及其制造方法。 一个这样的器件包括在源极/漏极区域的n +区域; 源/漏区的p +区; 以及在n +区域和p +区域之间的扩散阻挡材料。 n +区域基本上与p +区隔离。

公开(公告)号：US08698231B2

公开(公告)日：2014-04-15

申请号：US13600190

申请日：2012-08-30

申请人： Ki Hong Lee ,  Seung Ho Pyi ,  Jin Ho Bin

发明人： Ki Hong Lee ,  Seung Ho Pyi ,  Jin Ho Bin

IPC分类号： H01L21/20 ,  H01L29/78

CPC分类号： H01L27/11582

摘要： A semiconductor device includes vertical channel layers, a pipe channel layer coupling bottoms of the vertical channel layers, a pipe gate contacting a bottom surface and side surfaces of the pipe channel layer, and a dummy pipe gate formed of a non-conductive material and contacting a top surface of the pipe channel layer.

摘要翻译： 半导体器件包括垂直沟道层，连接垂直沟道层的底部的管道沟道层，与底部表面接触的管道和管道沟道层的侧表面，以及由非导电材料形成的虚拟管栅极和接触 管道通道层的顶表面。

公开(公告)号：US08604537B2

公开(公告)日：2013-12-10

申请号：US12493820

申请日：2009-06-29

申请人： Ki-Hong Lee ,  Kwon Hong

发明人： Ki-Hong Lee ,  Kwon Hong

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/792

摘要： There is provided a nonvolatile memory device having a tunnel dielectric layer formed over a substrate, the charge capturing layer formed over the tunnel dielectric layer and including a combination of at least one charge storage layer and at least one charge trap layer, a charge blocking layer formed over the charge capturing layer, and a gate electrode formed over the charge blocking layer.

摘要翻译： 提供了一种非易失性存储器件，其具有在衬底上形成的隧道介电层，所述电荷俘获层形成在所述隧道介电层上并包括至少一个电荷存储层和至少一个电荷俘获层，电荷阻挡层 形成在电荷捕获层上，以及形成在电荷阻挡层上的栅电极。

公开(公告)号：US20130153978A1

公开(公告)日：2013-06-20

申请号：US13598528

申请日：2012-08-29

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Seok Min JEON

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.

公开(公告)号：US08399323B2

公开(公告)日：2013-03-19

申请号：US13244247

申请日：2011-09-23

申请人： Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

发明人： Ki-Hong Lee ,  Moon-Sig Joo ,  Kwon Hong ,  Sun-Hwan Hwang

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/2236 ,  H01L27/11578 ,  H01L27/11582

摘要： A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

摘要翻译： 一种用于制造垂直通道型非易失性存储器件的方法，包括：在衬底上交替堆叠多个层间绝缘层和多个栅电极导电层; 蚀刻层间绝缘层和栅电极导电层以形成暴露衬底的沟槽; 在包括沟道沟槽的所得结构上形成未掺杂的第一沟道层; 通过等离子体掺杂工艺对具有杂质的第一沟道层进行掺杂; 以及用第二通道层填充沟槽。

公开(公告)号：US20130009229A1

公开(公告)日：2013-01-10

申请号：US13537650

申请日：2012-06-29

申请人： Ki Hong LEE ,  Seung Ho PYI ,  Jung Yun CHANG

发明人： Ki Hong LEE ,  Seung Ho PYI ,  Jung Yun CHANG

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/1037 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels.

摘要翻译： 半导体器件包括各自被配置为包括一对通道的存储器块，每个通道包括形成在存储器块的管道中的管道通道和与管道通道耦合的漏极侧通道和源极通道; 位于与其他存储块相邻的存储块之间的第一狭缝; 以及设置在每对通道的源极侧通道和漏极侧通道之间的第二狭缝。

公开(公告)号：USD658319S1

公开(公告)日：2012-04-24

申请号：US29373922

申请日：2011-06-08

申请人： Ki Hong Lee ,  Chi Young Kim

设计人： Ki Hong Lee ,  Chi Young Kim