公开(公告)号：US11922066B2

公开(公告)日：2024-03-05

申请号：US17576529

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Michael Raymond Miller ,  Steven C. Woo

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0673 ,  G11C7/1006

Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.

公开(公告)号：US11915136B1

公开(公告)日：2024-02-27

申请号：US17952852

申请日：2022-09-26

Applicant: Rambus Inc.

Inventor： Steven C. Woo

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: One or more neural network layers are implemented by respective sets of signed multiply-accumulate units that generate dual analog result signals indicative of positive and negative product accumulations, respectively. The two analog result signals and thus the positive and negative product accumulations are differentially combined to produce a merged analog output signal that constitutes the output of a neural node within the subject neural network layer.

公开(公告)号：US20240062788A1

公开(公告)日：2024-02-22

申请号：US18373162

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C7/1039 ,  G11C7/08 ,  G11C5/025 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/065 ,  G11C7/12 ,  G11C7/222 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US11907555B2

公开(公告)日：2024-02-20

申请号：US17989838

申请日：2022-11-18

Applicant: Rambus Inc.

Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0635 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/0673 ,  G06F13/1678 ,  Y02D10/00

Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

公开(公告)号：US11900981B2

公开(公告)日：2024-02-13

申请号：US18078934

申请日：2022-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F12/00 ,  G11C11/406 ,  G06F13/16

CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4067 ,  Y02D10/00

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

公开(公告)号：US20240045813A1

公开(公告)日：2024-02-08

申请号：US18236272

申请日：2023-08-21

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

IPC: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  H03K19/1778 ,  G11C7/10

CPC classification number: G06F13/16 ,  G11C5/02 ,  G11C5/04 ,  H03K19/1778 ,  G11C7/10

Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).

公开(公告)号：US11894093B2

公开(公告)日：2024-02-06

申请号：US17568649

申请日：2022-01-04

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/06 ,  H01L23/48 ,  H01L25/065 ,  H10B12/00 ,  G11C5/02

CPC classification number: G11C5/063 ,  G11C5/025 ,  H01L23/481 ,  H01L25/0657 ,  H10B12/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

公开(公告)号：US20240037055A1

公开(公告)日：2024-02-01

申请号：US18230375

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Steven C. WOO

IPC: G06F13/40 ,  H01L25/065 ,  G06N3/045

CPC classification number: G06F13/4027 ,  H01L25/0652 ,  G06N3/045

Abstract: Multiple device stacks are interconnected in a ring topology. The inter-device stack communication may utilize a handshake protocol. This ring topology may include the host so that the host may initialize and load the device stacks with data and/or commands (e.g., software, algorithms, etc.). The inter-device stack interconnections may also be configured to include/remove the host and/or to implement varying numbers of separate ring topologies. By configuring the system with more than one ring topology, and assigning different problems to different rings, multiple, possibly unrelated, machine learning tasks may be performed in parallel by the device stack system.

公开(公告)号：US11876652B2

公开(公告)日：2024-01-16

申请号：US17400823

申请日：2021-08-12

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Maruf H. Mohammad

IPC: H04L25/49 ,  H04L25/03

CPC classification number: H04L25/4917 ,  H04L25/03019 ,  H04L25/03178

Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.

公开(公告)号：US20240013819A1

公开(公告)日：2024-01-11

申请号：US18348716

申请日：2023-07-07

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Steven Woo ,  Craig Hampel ,  John Eric Linstadt

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/1006

Abstract: An apparatus and method for flexible metadata allocation and caching. In one embodiment of the method first and second requests are received from first and second applications, respectively, wherein the requests specify a reading of first and second data, respectively, from one or more memory devices. The circuit reads the first and second data in response to receiving the first and second requests. Receiving first and second metadata from the one or more memory devices in response to receiving the first and second requests. The first and second metadata correspond to the first and second data, respectively. The first and second data are equal in size, and the first and second metadata are unequal in size.