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    MULTI-TOUCH REMOTE CONTROL METHOD
    61.
    发明申请
    MULTI-TOUCH REMOTE CONTROL METHOD 审中-公开
    多触摸遥控方式

    公开(公告)号：US20160239201A1

    公开(公告)日：2016-08-18

    申请号：US14623874

    申请日：2015-02-17

    Applicant: Yu Albert WANG ,  Robin CHEUNG

    Inventor： Yu Albert WANG ,  Robin CHEUNG

    IPC: G06F3/0488 ,  G06F3/041 ,  H04N21/422 ,  G06F3/0354 ,  G06F3/01

    CPC classification number: G06F3/04883 ,  G06F3/03547 ,  G06F3/038 ,  G06F3/041 ,  G06F3/0416 ,  G06F2203/0381 ,  G06F2203/04808 ,  H04N21/42224

    Abstract: A multi-touch remote control method comprises following steps: a remote control device receiving a touch gesture input; computing a number of the touch points of the touch gesture input; generating and transferring a mouse event data to a receiving device as a mouse input if the number of the touch points is 1; and generating and transferring a single touch event data to the receiving device as a single touch input if the number of the touch points is greater than 1 and all the touch points of the touch gesture input are close to each other.

    Abstract translation: 多点遥控方法包括以下步骤：遥控装置接收触摸手势输入; 计算触摸手势输入的触摸点的数量; 如果触摸点的数量为1，则将鼠标事件数据作为鼠标输入生成并传送到接收设备; 以及如果触摸点的数量大于1并且触摸手势输入的所有触摸点彼此接近，则将单个触摸事件数据生成并传送到接收设备作为单个触摸输入。

    Continuous plane of thin-film materials for a two-terminal cross-point memory
    64.
    发明授权
    Continuous plane of thin-film materials for a two-terminal cross-point memory 失效
    用于两端交叉点存储器的薄膜材料的连续平面

    公开(公告)号：US07742323B2

    公开(公告)日：2010-06-22

    申请号：US11881474

    申请日：2007-07-26

    Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

    Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Travis Byonghyop Oh

    IPC: G11C11/00

    CPC classification number: H01L27/101 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1641 ,  H01L45/165 ,  Y10S257/903

    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

    Abstract translation: 公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。 薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。 施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。 存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。 为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。 存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。 包层导体可以包括由铜制成的芯材料。

    Protective layer for a low k dielectric film and methods of forming the same
    65.
    发明申请
    Protective layer for a low k dielectric film and methods of forming the same 审中-公开
    低k电介质膜的保护层及其形成方法

    公开(公告)号：US20070254491A1

    公开(公告)日：2007-11-01

    申请号：US11413715

    申请日：2006-04-29

    Applicant: Robin Cheung

    Inventor： Robin Cheung

    IPC: H01L23/58 ,  H01L21/31

    CPC classification number: H01L21/3105 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76835

    Abstract: A semiconductor stack having a protective layer formed into a low k dielectric material is provided. The method for forming the protective layer in a low k dielectric material may include plasma etching the low k dielectric material to form Si—OH bonds on a surface of the low k dielectric material, exposing the Si—OH bonds to a silicon containing fluid solution, and replacing the Si—OH bonds with Si—Si bonds generated by the silicon containing fluid solution to form a protective layer on the surface of the low k dielectric material.

    Abstract translation: 提供了具有形成为低k电介质材料的保护层的半导体叠层体。 用于在低k电介质材料中形成保护层的方法可以包括等离子体蚀刻低k电介质材料以在低k电介质材料的表面上形成Si-OH键，将Si-OH键暴露于含硅流体溶液 并且用由含硅流体溶液产生的Si-Si键代替Si-OH键，以在低k电介质材料的表面上形成保护层。

    Semiconductor device interconnect fabricating techniques
    68.
    发明申请
    Semiconductor device interconnect fabricating techniques 失效
    半导体器件互连制造技术

    公开(公告)号：US20060063370A1

    公开(公告)日：2006-03-23

    申请号：US10945664

    申请日：2004-09-21

    Applicant: Robin Cheung ,  Ashok Sinha

    Inventor： Robin Cheung ,  Ashok Sinha

    IPC: H01L21/4763 ,  H01L21/44

    CPC classification number: H01L21/76885 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76852 ,  H01L2221/1089

    Abstract: The present invention provides methods for fabricating integrated circuit structures for use in semiconductor wafer fabrication techniques. A Cu diffusion barrier/Cu seed sandwich layer is deposited on a substrate. A first sacrificial layer, deposited on the sandwich layer, is developed to form a cavity. A first Cu layer is selectively deposited on the sandwich layer inside the cavity. A second sacrificial layer is deposited on the first sacrificial layer and on the first Cu layer. A cavity is formed in the second sacrificial layer, exposing at least a portion of the first Cu layer. A second Cu layer is selectively deposited in the second sacrificial layer cavity including the exposed portion of the first Cu layer. The combination of the first and second Cu layers forms a Cu component. Subsequently, the first and second sacrificial layers are removed resulting in a Cu component that is free standing on the sandwich layer, such that the top and sides of the component are exposed. Sandwich layer portions extending from the Cu component are removed from the substrate, thereby forming an exposed sandwich layer edge between the surface of the Cu component and the substrate. A Cu diffusion barrier layer is deposited on the Cu component and on the exposed edge of the sandwich layer, resulting in a Cu barrier layer encapsulated component. The encapsulated component is encased in a dielectric layer. Similarly, Cu components of the present invention are fabricated by means of selective electroless Cu deposition in a sacrificial layer cavity having a metal layer that is formed by selective electroless deposition of a metal on a sensitizer layer. Examples of Cu components and encapsulated Cu components of the present invention include vertical interconnects and inverted damascene structures.

    Abstract translation: 本发明提供用于制造用于半导体晶片制造技术的集成电路结构的方法。 在基底上沉积Cu扩散阻挡层/ Cu种子夹层。 沉积在夹心层上的第一牺牲层被开发以形成空腔。 第一Cu层被选择性地沉积在空腔内的夹层上。 在第一牺牲层和第一Cu层上沉积第二牺牲层。 在第二牺牲层中形成空腔，露出第一Cu层的至少一部分。 第二Cu层被选择性地沉积在包括第一Cu层的暴露部分的第二牺牲层腔中。 第一和第二Cu层的组合形成Cu组分。 随后，去除第一和第二牺牲层，导致在夹层上自由站立的Cu成分，使得部件的顶部和侧面被暴露。 从基板上除去从Cu成分延伸的夹层，从而在Cu成分的表面与基板之间形成露出的夹层结构。 在Cu组分和夹层的暴露边缘上沉积Cu扩散阻挡层，形成Cu阻挡层封装组分。 封装的组件被封装在电介质层中。 类似地，本发明的Cu组分通过选择性无电镀Cu沉积在具有金属层的牺牲层腔中制造，所述金属层通过金属在敏化剂层上的选择性无电沉积形成。 本发明的Cu组分和包封的Cu组分的实例包括垂直互连和反向镶嵌结构。

    Post metal barrier/adhesion film
    69.
    发明授权
    Post metal barrier/adhesion film 有权
    后金属屏障/粘合膜

    公开(公告)号：US06753248B1

    公开(公告)日：2004-06-22

    申请号：US10352505

    申请日：2003-01-27

    Applicant: Michael Wood ,  Barry L. Chin ,  Paul F. Smith ,  Robin Cheung

    Inventor： Michael Wood ,  Barry L. Chin ,  Paul F. Smith ,  Robin Cheung

    IPC: H01L214763

    CPC classification number: H01L21/76852 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76885

    Abstract: A method for processing a substrate. The method generally includes forming a copper interconnect in a sacrificial layer deposited on the substrate by patterning the sacrifical layer to form an interconnect and filling the interconnect with copper. The method additionally includes removing at least a portion of the sacrificial layer upon copper interconnect formation, depositing a barrier layer on the copper interconnect, and depositing a dielectric layer on the barrier layer.

    Abstract translation: 一种处理衬底的方法。 该方法通常包括通过图案化牺牲层以形成互连并用铜填充互连件在沉积在衬底上的牺牲层中形成铜互连。 该方法还包括在铜互连形成时去除牺牲层的至少一部分，在铜互连上沉积阻挡层，以及在阻挡层上沉积电介质层。

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