公开(公告)号：US20130055192A1

公开(公告)日：2013-02-28

申请号：US13611609

申请日：2012-09-12

Applicant: John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

Inventor： John L. Colbert ,  Arvind K. Sinha ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: H05K1/144 ,  G11C5/025 ,  H05K1/113 ,  H05K1/114 ,  H05K1/141 ,  H05K3/0058 ,  H05K3/325 ,  H05K2201/044 ,  H05K2201/10378 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2009

Abstract: Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB.

Abstract translation: 提供了在PCB之间互连和分配信号和电源的机制。 提供了具有地面栅格阵列（LGAs）的第一PCB和为第一PCB上的互连部件设计的第一布线层以及用于将部件连接到第二PCB的第二布线层。 第二PCB具有相对的平行的第一和第二表面，第一表面具有LGA。 设置用于互连第二PCB上的组件的布线层和用于将第二PCB上的组件与第一PCB上的组件互连的层。 第一插入器耦合到第一PCB的第一表面的LGA并将部件连接到第一PCB。 第二插入件夹在第一PCB的第二表面的LGA和第二PCB的第一表面的LGA之间并耦合到第二PCB的第二表面的LGA。

公开(公告)号：US20120120576A1

公开(公告)日：2012-05-17

申请号：US12945111

申请日：2010-11-12

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: G06F1/16 ,  H05K7/02

CPC classification number: H05K7/1061 ,  G06F1/183 ,  H01L2924/15311

Abstract: A processor module socket accommodates processor modules of different sizes with adapters that align smaller-sized modules so that module pins align with desired contact points. The largest supported processor module engages with the socket in a conventional manner without the use of an adapter. Smaller processor modules engage within an adapter that in turn engages in the socket in a manner similar to the largest supported processor module. The contact points of the socket support different sized processor modules by keying logical functions based upon the type of processor module installed in the socket.

Abstract translation: 处理器模块插座可容纳具有不同尺寸的处理器模块，适配器可对准较小尺寸的模块，使模块引脚与所需的接触点对准。 最大的支持的处理器模块以常规方式与插座接合，而不使用适配器。 较小的处理器模块接合在适配器中，该适配器又以类似于最大支持的处理器模块的方式进入插座。 插座的接点通过根据安装在插座中的处理器模块的类型键入逻辑功能来支持不同大小的处理器模块。

公开(公告)号：US20120081142A1

公开(公告)日：2012-04-05

申请号：US12894325

申请日：2010-09-30

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: H03K19/00

CPC classification number: H01L27/0203 ,  B23K26/38 ,  B23K2101/38

Abstract: A function of an integrated circuit is selectively disabled by mechanical intervention at a module that contains the integrated circuit, such as drilling a hole through the module, cutting a slot in the module or burning a hole with a laser through the laser. Mechanical destruction of the module at a predetermined spot disrupts a function enable signal that is otherwise provide through wires of the module to a connection with the integrated circuit. Without the function enable signal from the module wires to the integrated circuit connector, the function associated with the function enable signal cannot run on the integrated circuit.

Abstract translation: 集成电路的功能通过在包含集成电路的模块上的机械干预来选择性地禁用，例如在模块中钻孔，切割模块中的槽或通过激光器用激光烧孔。 在预定点处的模块的机械破坏破坏了另外通过模块的导线与集成电路的连接提供的功能使能信号。 没有功能使能信号从模块导线到集成电路连接器，与功能使能信号相关的功能不能在集成电路上运行。

公开(公告)号：US20110267602A1

公开(公告)日：2011-11-03

申请号：US12771245

申请日：2010-04-30

Applicant: Kevin J. Bills ,  Mahesh Bohra ,  Hong T. Dang ,  Rohan U. Mandrekar ,  Roger D. Weekly

Inventor： Kevin J. Bills ,  Mahesh Bohra ,  Hong T. Dang ,  Rohan U. Mandrekar ,  Roger D. Weekly

IPC: G01N21/84

CPC classification number: G01M11/3154

Abstract: For testing whether an optical fiber is properly connected to a device, a beam of light is output to the optical fiber. An intensity is detected of light reflected by the device back through the optical fiber in response to the beam of light. In response to the detected intensity, a determination is made of whether the optical fiber is properly connected to the device.

Abstract translation: 为了测试光纤是否正确连接到设备，光束被输出到光纤。 通过响应于光束，通过光纤反射的装置反射的光的强度被检测。 响应于检测到的强度，确定光纤是否正确连接到设备。

公开(公告)号：US07821796B2

公开(公告)日：2010-10-26

申请号：US12015543

申请日：2008-01-17

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H05K1/11

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Reference plane voids with a strip segment for improving transmission line integrity over vias permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有用于改善通孔上的传输线完整性的带段的参考平面空隙允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

公开(公告)号：US07818599B2

公开(公告)日：2010-10-19

申请号：US11869186

申请日：2007-10-09

Applicant: Anand Haridass ,  Colm B. O'Reilly ,  Roger D. Weekly

Inventor： Anand Haridass ,  Colm B. O'Reilly ,  Roger D. Weekly

IPC: G06F1/26

CPC classification number: G06F1/28

Abstract: A circuit and a method for detecting noise events in a system with time variable operating points is provided. A switched capacitor filter comprising a plurality of capacitor units, samples a first voltage to determine an average of a set of voltage measurements, forming an average voltage. A filter control unit controls the plurality of capacitor units in the switched capacitor filter. A comparing unit compares the average voltage to the first voltage to form a comparison. A signaling unit generates a signal to instruct circuits in a processor to initiate actions to keep the first voltage from drooping below a threshold level in response to the comparison.

Abstract translation: 提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路和方法。 一种开关电容滤波器，包括多个电容器单元，对第一电压进行采样，以确定一组电压测量的平均值，形成平均电压。 滤波器控制单元控制开关电容滤波器中的多个电容器单元。 比较单元将平均电压与第一电压进行比较以形成比较。 信号单元产生信号以指示处理器中的电路响应于比较而发起动作以使第一电压不会下降到低于阈值水平。

公开(公告)号：US07786579B2

公开(公告)日：2010-08-31

申请号：US11752449

申请日：2007-05-23

Applicant: Jean Audet ,  Anson J. Call ,  Steven P. Ostrander ,  Douglas O. Powell ,  Roger D. Weekly

Inventor： Jean Audet ,  Anson J. Call ,  Steven P. Ostrander ,  Douglas O. Powell ,  Roger D. Weekly

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/116 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K2201/09454 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A microelectronic package having integrated circuits is provided. The microelectronic package includes multiple dielectric laminate layers, copper circuitry between the dielectric laminate layers where the copper circuitry includes circuit traces, and ball grid arrays/land grid arrays operatively connected to the copper circuitry such that conduction occurs. Further, proximate to the connection of the copper circuitry and the ball grid arrays/land grid arrays, a protective copper tongue is below an extension of the circuit traces, such that the protective copper tongue prevents the circuit traces from being affected by cracking propagated in the dielectric laminate layers or the ball grid arrays/land grid arrays.

Abstract translation: 提供具有集成电路的微电子封装。 微电子封装包括多个电介质层压层，铜电路在介电层压层之间，其中铜电路包括电路迹线，以及球栅阵列/焊盘电极阵列，可操作地连接到铜电路，从而导通发生。 此外，靠近铜电路和球栅阵列/接地栅阵列的连接，保护铜舌低于电路迹线的延伸线，使得保护铜舌防止电路迹线受到在 电介质层压层或球栅阵列/焊盘阵列。

公开(公告)号：US07599808B2

公开(公告)日：2009-10-06

申请号：US11848380

申请日：2007-08-31

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: G01R19/00

CPC classification number: G06F1/3203 ,  G06F1/28 ,  G06F1/305 ,  G06F1/3237 ,  Y02D10/128

Abstract: A method and system for applying multiple voltage droop detection and instruction throttling instances with customized thresholds across semiconductor chips. Environmental parameters are detected for various locations on a chip, and timing margins are determined for each location on the chip. An acceptable voltage droop for each location is determined based on the environmental parameters and the timing margins for the corresponding location. A droop threshold is then determined for each location based on the corresponding acceptable voltage droop determined for the corresponding location.

Abstract translation: 一种用于跨半导体芯片应用具有定制阈值的多个电压下降检测和指令调节实例的方法和系统。 检测芯片上各个位置的环境参数，并为芯片上的每个位置确定定时裕度。 基于相应位置的环境参数和定时裕度来确定每个位置的可接受电压下降。 然后基于为相应位置确定的相应的可接受电压下降，为每个位置确定下垂阈值。

公开(公告)号：US20090184784A1

公开(公告)日：2009-07-23

申请号：US12015543

申请日：2008-01-17

Applicant: Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

Inventor： Sungjun Chun ,  Anand Haridass ,  Roger D. Weekly

IPC: H01P1/00 ,  H05K3/00

CPC classification number: G06F17/5077 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24322

Abstract: Reference plane voids with a strip segment for improving transmission line integrity over vias permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract translation: 具有用于改善通孔上的传输线完整性的带段的参考平面空隙允许在通孔上路由关键信号路径，同时仅通过插入电容略微增加。 传输线参考平面定义了通过刚性衬底芯的信号承载电镀通孔（PTH）上方（或下方）的空隙，使得信号不会被阻抗失配降级，否则会由分流电容引起 信号承载PTH的顶部（或底部）到传输线参考平面。 为了提供增加的布线密度，信号路径被布置在空隙上，但是通过将导电条包括通过空隙来防止由空隙引起的信号路径的破坏，从而减小与信号承载PTH的耦合并维持 信号路径导体。

公开(公告)号：US20090063884A1

公开(公告)日：2009-03-05

申请号：US11847557

申请日：2007-08-30

Applicant: Roger D. Weekly

Inventor： Roger D. Weekly

IPC: G06F11/30

CPC classification number: G06F1/3203 ,  G06F1/329 ,  Y02D10/24

Abstract: A method and system for applying multiple voltage droop detection and instruction throttling instances with customized thresholds across semiconductor chips. Environmental parameters are detected for various locations on a chip, and timing margins are determined for each location on the chip. An acceptable voltage droop for each location is determined based on the environmental parameters and the timing margins for the corresponding location. A droop threshold is then determined for each location based on the corresponding acceptable voltage droop determined for the corresponding location.