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公开(公告)号：US09116639B2
公开(公告)日：2015-08-25
申请号：US13717978
申请日：2012-12-18
Applicant: Apple Inc.
Inventor： Brijesh Tripathi
CPC classification number: G06F1/12 , G09G5/006 , G09G5/008 , G09G5/12 , G09G2330/021 , G09G2340/0435 , G09G2360/18 , G09G2370/047 , G09G2370/10
Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.
Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路，辅助链路和热插拔检测链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令。 源处理器可以经由主链路将初始化参数发送到宿处理器。 初始化参数可以包括时钟数据恢复锁定参数和空闲参数。 在初始化参数之后，源处理器可以经由主链路向宿处理器发送同步信号。 然后，源处理器可以经由主链路向宿处理器发送睡眠命令。
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公开(公告)号：US20150093023A1
公开(公告)日：2015-04-02
申请号：US14042447
申请日：2013-09-30
Applicant: Apple Inc.
Inventor： Kenneth Greenebaum , Ian Hendry , Ian Ollmann , David Hayward , Brijesh Tripathi
IPC: G06T9/00 , H04N19/463 , H04N19/85
CPC classification number: H04N19/85 , G06T9/00 , G11B27/034 , H04N19/186 , H04N19/30 , H04N19/33 , H04N19/463 , H04N21/234327 , H04N21/2662 , H04N21/845
Abstract: Techniques are provided for encoding an extended image such that it is backwards compatible with existing decoding devices. An extended image format is defined such that the extended image format is consistent with an existing image format over the full range of the existing image format. Because the extended image format is consistent with the existing image format over the full range of the existing image format, additional image information that is included in an extended image can be extracted from the extended image. A base version of an image (expressed using the existing image format) may be encoded in a payload portion and the extracted additional information may be stored in a metadata portion of a widely supported image file format.
Abstract translation: 提供了用于对扩展图像进行编码的技术，使得其与现有的解码装置向后兼容。 定义扩展图像格式，使得扩展图像格式与现有图像格式的全部范围内的现有图像格式一致。 由于扩展图像格式与现有图像格式的全部范围内的现有图像格式一致，所以可以从扩展图像中提取包含在扩展图像中的附加图像信息。 图像的基本版本（使用现有图像格式表示）可以被编码在有效载荷部分中，并且所提取的附加信息可以存储在广泛支持的图像文件格式的元数据部分中。
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公开(公告)号：US20150062134A1
公开(公告)日：2015-03-05
申请号：US14017742
申请日：2013-09-04
Applicant: Apple Inc.
Inventor： Peter F. Holland , Brijesh Tripathi , Hao Chen
CPC classification number: G09G5/00 , G06F5/10 , G09G5/363 , H04N5/00 , H04N5/14 , H04N7/025 , H04N7/0884
Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve a top frame packet from the parameter buffer and determine if the frame packet is an internal type, i.e., intended for internal registers in a respective processing unit or if it is an external type, i.e., intended for an external register elsewhere in the graphics system. Based on the type of frame packet, the control circuit may update one or more register values accordingly.
Abstract translation: 图形系统可以包括用于处理当前显示帧的一个或多个处理单元，每个处理单元包括用于存储用于处理当前显示帧的参数设置的多个参数寄存器。 图形系统中的参数缓冲器可以存储帧分组，每个帧分组包含对应于要用于至少一个显示帧的参数设置的信息。 耦合到缓冲器和一个或多个处理单元的控制电路可以从参数缓冲器检索顶部帧分组，并且确定帧分组是否是内部类型，即针对相应处理单元中的内部寄存器，或者如果它 是一种外部类型，即用于图形系统中其他地方的外部寄存器。 基于帧分组的类型，控制电路可以相应地更新一个或多个寄存器值。
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64.发明申请公开(公告)号：US20140292787A1
公开(公告)日：2014-10-02
申请号：US13850548
申请日：2013-03-26
Applicant: APPLE INC.
Inventor： Brijesh Tripathi , Peter F. Holland , Albert C. Kuo
IPC: G09G5/395
CPC classification number: G09G5/395 , G06F3/14 , G09G5/001 , G09G5/393 , G09G2330/02 , G09G2330/021 , G09G2340/02 , G09G2360/121
Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.
Abstract translation: 在一个实施例中，显示管被配置为组合一个或多个图像帧和/或视频序列以产生用于显示的输出帧。 此外，显示管可以被配置为压缩输出帧并且响应于检测到输出帧中的静态内容而将压缩帧写入存储器。 显示管还可以被配置为从存储器读取压缩帧用于显示，而不是读取用于合成和显示的帧。 在一些实施例中，显示管道可以包括被配置为监视显示管道和/或输出框架的操作以检测静态内容的空闲屏幕检测电路。
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公开(公告)号：US08838859B2
公开(公告)日：2014-09-16
申请号：US14218011
申请日：2014-03-18
Applicant: Apple Inc.
Inventor： Anup K. Sharma , Scott P. Krueger , James M. Hollabaugh , Roberto G. Yepez , Brijesh Tripathi , Jeffrey J. Terlizzi , Terry L. Tikalsky
CPC classification number: G06F3/1431 , G06F3/14 , G06F13/385 , G06F13/4013 , G06F13/4018 , G06T1/60 , Y02D10/14 , Y02D10/151
Abstract: In an embodiment, a host computing device includes an internal display and also includes a connector to connect to an external display. A cable is provided to connect to the connector and to connect to the external display. The cable includes video processing capabilities. For example, the cable may include a memory configured to store a frame buffer. The frame buffer may store a frame of video data for further processing by the video processing device in the cable. The video processing device may manipulate the frame in a variety of ways, e.g. scaling, rotating, gamma correction, dither correction, etc.
Abstract translation: 在一个实施例中，主计算设备包括内部显示器，并且还包括连接到外部显示器的连接器。 提供电缆连接到连接器并连接到外部显示器。 电缆包括视频处理功能。 例如，电缆可以包括被配置为存储帧缓冲器的存储器。 帧缓冲器可以存储视频数据的帧，以供视频处理设备在电缆中进一步处理。 视频处理设备可以以各种方式来操纵帧，例如， 缩放，旋转，伽马校正，抖动校正等
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Patent Agency Ranking
公开(公告)号：US20140253570A1
公开(公告)日：2014-09-11
申请号：US13788209
申请日：2013-03-07
Applicant: APPLE INC.
Inventor： Brijesh Tripathi , Peter F. Holland , Timothy J. Millet
IPC: G06T1/60
CPC classification number: G06T1/60 , G09G5/006 , G09G2340/0442 , G09G2340/0492 , G09G2360/125 , G09G2370/10
Abstract: In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation.
Abstract translation: 在一个实施例中，系统包括针对与网络显示器进行通信而优化的硬件。 硬件可以包括显示管单元，其被配置为将来自视频序列的一个或多个静态图像和一个或多个帧组合以形成用于由网络显示器显示的帧。 显示管单元可以包括写回单元，其被配置为将复合帧写回到存储器，可以使用视频编码器硬件来选择性地对帧进行编码，并将其分组化以便通过网络传输到网络显示器。 在一个实施例中，显示管单元可以被配置为在帧的生成期间向视频编码器发出中断，以重叠编码和帧生成。
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67.发明授权公开(公告)号：US12117320B2
公开(公告)日：2024-10-15
申请号：US17366459
申请日：2021-07-02
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal , Michael F. Culbert
IPC: G01D9/00 , A61G3/06 , B60P1/43 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/16
CPC classification number: G01D9/00 , A61G3/061 , B60P1/433 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/00 , Y02D30/50
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when a central processing unit (CPU) processor and a memory controller of the SOC are powered off. The component may include a sensor capture unit to capture audio samples from an audio detector circuit and write them to a memory of the component. A processor of the component may be configured to search the audio samples for a predetermined pattern during a time when the CPU processor and the memory controller are powered down. In some embodiments, based on the audio samples filling to a threshold level in the memory of the component and a lack of detection of the predetermined pattern, the component is configured to wake up the memory controller and a path to the memory controller in order to write the audio sample to a memory controlled by the memory controller.
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公开(公告)号：US11068088B2
公开(公告)日：2021-07-20
申请号：US16802349
申请日：2020-02-26
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Jean-Pierre S. Guillou
Abstract: An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.
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公开(公告)号：US10592021B2
公开(公告)日：2020-03-17
申请号：US16028377
申请日：2018-07-05
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Jean-Pierre S. Guillou
Abstract: An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.
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公开(公告)号：US20180313673A1
公开(公告)日：2018-11-01
申请号：US16019087
申请日：2018-06-26
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G01D9/00 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/122 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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