公开(公告)号：US20140328131A1

公开(公告)日：2014-11-06

申请号：US14332650

申请日：2014-07-16

Applicant: Apple Inc.

Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.

Abstract translation: 一种方法包括选择用于在与相应字线相关联的行中排列的模拟存储器单元阵列中编程的字线，所述行与相应位线相关联。 对所选字线中的存储单元进行编程的字线电压被施加到相应的字线。 将所选择的字线外部的一个或多个附加存储单元作为所选字线编程的结果编程的位线电压被施加到相应的位线。 使用所应用的字线和位线电压，将数据存储在所选字线中的存储单元中，并且附加存储单元被同时编程。

公开(公告)号：US08862964B2

公开(公告)日：2014-10-14

申请号：US14147714

申请日：2014-01-06

Applicant: Apple Inc.

Inventor： Avraham Meir ,  Micha Anholt ,  Naftali Sommer ,  Eyal Gurgi

IPC: G11C29/00 ,  G11C27/00 ,  G06F11/10 ,  G11C16/04 ,  G11C16/12

CPC classification number: G11C27/005 ,  G06F11/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5647 ,  G11C2211/5648

Abstract: A method for data storage includes, in a first programming phase, storing first data in a group of analog memory cells by programming the memory cells in the group to a set of initial programming levels. In a second programming phase that is subsequent to the first programming phase, second data is stored in the group by: identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels; and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels.

Abstract translation: 一种用于数据存储的方法包括在第一编程阶段通过将该组中的存储器单元编程为一组初始编程级别来将第一数据存储在一组模拟存储器单元中。 在第一编程阶段之后的第二编程阶段，通过以下方式将第二数据存储在组中：将在第一编程阶段中编程的组中的存储器单元识别为初始编程的预定义部分子集中的相应电平 水平; 以及仅使用所述第二数据来编程所识别的存储器单元，以便将所识别的存储器单元中的至少一些设置为与所述初始编程级别不同的一个或多个附加编程级别。

公开(公告)号：US20140160866A1

公开(公告)日：2014-06-12

申请号：US13709303

申请日：2012-12-10

Applicant: APPLE INC.

Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

IPC: G11C7/00

CPC classification number: G11C27/00 ,  G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.

Abstract translation: 一种方法包括在与各个字线相关联的行中排列的模拟存储器单元的阵列中，读取选定字线中的第一组存储器单元，包括存储至少一个状态的一个或多个存储器单元 数组中除字线以外的所选字线。 响应于读取状态设置第二组存储器单元的读出配置。 使用读出配置读取第二组存储单元。

公开(公告)号：US20140160865A1

公开(公告)日：2014-06-12

申请号：US13709267

申请日：2012-12-10

Applicant: APPLE INC.

Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.

公开(公告)号：US20140157084A1

公开(公告)日：2014-06-05

申请号：US14090431

申请日：2013-11-26

Applicant: Apple Inc.

Inventor： Ofir Shalvi ,  Naftali Sommer ,  Eyal Gurgi ,  Ariel Maislos

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1016 ,  G11C16/26

Abstract: A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.

Abstract translation: 用于操作存储器（28）的方法包括将存储器的一组模拟存储器单元（32）中的数据存储为相应的第一电压电平。 在存储数据之后，从相应的模拟存储器单元读取第二电压电平。 第二电压电平受到交叉耦合干扰的影响，导致第二电压电平与相应的第一电压电平不同。 通过处理第二电压电平来估计量化模拟存储器单元之间的交叉耦合干扰的交叉耦合系数。 使用估计的交叉耦合系数，从读取的第二电压电平重建存储在模拟存储器单元组中的数据。

公开(公告)号：US20130121080A1

公开(公告)日：2013-05-16

申请号：US13734335

申请日：2013-01-04

Applicant: Apple Inc.

Inventor： Naftali Sommer ,  Ofir Shalvi ,  Uri Perlmutter ,  Oren Golov ,  Eyal Gurgi ,  Micha Anholt ,  Dotan Sokolov

IPC: G11C16/04

CPC classification number: G11C16/04 ,  G11C8/20 ,  G11C11/5642 ,  G11C16/20 ,  G11C16/28 ,  G11C2211/5634

Abstract: A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. A memory access operation is performed on the cells using the one or more thresholds.

Abstract translation: 一种用于操作包括多个模拟存储单元（32）的存储器（28）的方法包括：通过向单元写入第一存储值来将数据存储在存储器中。 从单元读取第二存储值，并且估计第二存储值的累积分布函数（CDF）。 处理估计的CDF以计算一个或多个阈值。 使用一个或多个阈值对单元执行存储器存取操作。

公开(公告)号：US20200257598A1

公开(公告)日：2020-08-13

申请号：US16271907

申请日：2019-02-11

Applicant: Apple Inc.

Inventor： Eli Yazovitsky ,  Eyal Gurgi ,  Michael Tsohar

IPC: G06F11/20

Abstract: A controller includes an interface and storage circuitry. The interface communicates with a memory that includes memory cells that store data in multiple programming levels, and that are organized in Word Lines (WLs). Each WL connects to one or more cell-groups of the memory cells. The memory cells in some cell-groups suffer from an impairment that has a different severity for reading data units of different bit-significance values. The storage circuitry assigns multiple parity groups to data units stored in cell-groups belonging to consecutive WLs, so that a same parity group is assigned to data units of different bit-significance values in neighboring groups of Nwl consecutive WLs. Upon detecting a failure to access a data unit of a given parity group, due to the impairment, the storage circuitry recovers the data unit using other data units assigned to the given parity group, and that are stored in other cell-groups.

公开(公告)号：US20200053108A1

公开(公告)日：2020-02-13

申请号：US16057732

申请日：2018-08-07

Applicant: APPLE INC.

Inventor： Gencer Cili ,  Sairam T. Gutta ,  Eyal Gurgi ,  Moshe Neerman ,  Mor Doron ,  Franco Travostino ,  Naftali Sommer

IPC: H04L29/06 ,  G06F11/07 ,  G06K9/62 ,  G06N99/00 ,  G06F17/30

Abstract: The subject technology receives an input data set including rows of values for features of the input data set, each row including a different combination of values for the features. The subject technology classifies one or more rows of values as an anomaly based on anomaly scores determined for each of the rows of values. The subject technology determines a subset of the different features that affect the anomaly scores of the one or more rows classified as the anomaly. The subject technology determines a root cause for at least one of the rows classified as the anomaly based on values of the subset of the different features for the at least one of the rows. The subject technology provides an indication of the root cause to a device to enable the device to perform an action when encountering conditions corresponding to the root cause at a subsequent time.

公开(公告)号：US10353769B2

公开(公告)日：2019-07-16

申请号：US15658433

申请日：2017-07-25

Applicant: Apple Inc.

Inventor： Charan Srinivasan ,  Eyal Gurgi

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/08

Abstract: A storage system includes an interface and storage circuitry. The interface is configured to communicate with a plurality of memory cells coupled to multiple Bit Lines (BLs). The memory cells are programmed and read in sub-groups of multiple BLs, and the sub-groups correspond to respective addresses. The storage circuitry is configured to generate a sequence of addresses for reading memory cells that together store a data part and a pattern part containing a predefined pattern, via multiple respective sub-groups, to detect that the data part read from the memory cells is erroneous due to a fault that occurred in the sequence of addresses by identifying a mismatch between the pattern part read from the memory cells and the predefined pattern, and, in response to detecting the fault, to take a corrective measure to recover an error-free version of the data part.

公开(公告)号：US10115476B2

公开(公告)日：2018-10-30

申请号：US15221947

申请日：2016-07-28

Applicant: Apple Inc.

Inventor： Eyal Gurgi ,  Yoav Kasorla ,  Barak Rotbard ,  Shai Ojalvo

IPC: G06F11/07 ,  G06F11/263 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00 ,  G11C16/10 ,  G11C16/34 ,  G11C29/12 ,  G11C29/38 ,  G11C29/44 ,  G11C29/50

Abstract: A method for data storage includes receiving in a memory device data for storage in a group of memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.