公开(公告)号：US20170168520A1

公开(公告)日：2017-06-15

申请号：US14965073

申请日：2015-12-10

Applicant: Apple Inc.

Inventor： Shu-Yi Yu ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Kiran B. Kattel ,  Manu Gulati

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G06F1/14

Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

公开(公告)号：US09659616B2

公开(公告)日：2017-05-23

申请号：US14459466

申请日：2014-08-14

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Erik P. Machnicki ,  Gilbert H. Herbeck

IPC: G11C17/16 ,  G11C7/20 ,  G11C29/04 ,  G11C29/44

CPC classification number: G11C7/20 ,  G11C17/16 ,  G11C2029/0407 ,  G11C2029/4402

Abstract: In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode.

公开(公告)号：US20160077579A1

公开(公告)日：2016-03-17

申请号：US14486491

申请日：2014-09-15

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Tristan R. Hudson ,  Parin Patel ,  Fabien Faure

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/30 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a system includes a power management unit (PMU), a non-volatile memory, a volatile memory, and a processor. The PMU may be configured to generate a power supply voltage, change a state of a status signal responsive to an event, and reduce a voltage level of the power supply voltage responsive to a predetermined period of time elapsing from detecting the event. The system may be configured to transition from a first to a second operating mode responsive to the change of the state of the status signal, and cancel pending commands to the non-volatile memory responsive to the transition to the second operating mode. The non-volatile memory may be configured to complete active commands prior the predetermined period of time elapsing.

Abstract translation: 在一个实施例中，系统包括电源管理单元（PMU），非易失性存储器，易失性存储器和处理器。 PMU可以被配置为产生电源电压，响应于事件改变状态信号的状态，并且响应于从检测到事件经过的预定时间段来降低电源电压的电压电平。 系统可以被配置为响应于状态信号的状态的改变而从第一操作模式转换到第二操作模式，并且响应于转换到第二操作模式而将待决命令取消到非易失性存储器。 非易失性存储器可以被配置为在经过预定时间段之前完成活动命令。

公开(公告)号：US20160055110A1

公开(公告)日：2016-02-25

申请号：US14467164

申请日：2014-08-25

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Munetoshi Fukami ,  Manu Gulati

IPC: G06F13/40 ,  G06F1/32

CPC classification number: G06F13/4022 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed.

Abstract translation: 公开了用于片上通信网络的事务过滤器。 在一个实施例中，集成电路（IC）包括多个功能电路块，其中一些可以被置于休眠模式（例如，电源门控）。 IC还包括多个事务过滤器，每个事务过滤器都与唯一的一个功能电路块相关联。 响应于其相关联的功能电路块生成事务，给定的事务过滤器可以确定事务处理的功能电路块是否处于睡眠模式。 如果确定事务发往当前处于睡眠模式的功能电路块，则事务过滤器可以阻止该事务被传送。

公开(公告)号：US20160049207A1

公开(公告)日：2016-02-18

申请号：US14459466

申请日：2014-08-14

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Erik P. Machnicki ,  Gilbert H. Herbeck

IPC: G11C17/18 ,  G11C7/20 ,  G11C17/16

CPC classification number: G11C7/20 ,  G11C17/16 ,  G11C2029/0407 ,  G11C2029/4402

Abstract: In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode.

Abstract translation: 在一个实施例中，装置可以包括多个电路块，多个保险丝和电路。 电路可以被配置为响应于从关闭模式转换到第一操作模式来确定多个保险丝中的每一个的状态。 可以在第一操作模式中启用第一数量的电路块。 电路还可以被配置为根据多个保险丝中的一个或多个保险丝的状态并从第一操作模式转换到第二操作模式来初始化第一数量的电路块。 可以在第二操作模式中使能小于第一数量的第二数量的电路块。 电路还可以被配置为将表示多个保险丝的子集的状态的数据存储到在第二操作模式中启用的第一存储器中。

公开(公告)号：US09201821B2

公开(公告)日：2015-12-01

申请号：US13629509

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Josh P. de Cesare ,  Manu Gulati

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A system and method for maintaining accurate interrupt timestamps. A semiconductor chip includes an interrupt controller (IC) with an interface to multiple sources of interrupts. In response to receiving an interrupt, the IC copies and records the value stored in a main time base counter used for maintaining a global elapsed time. The IC sends an indication of the interrupt to a corresponding processor. Either an interrupt service routine (ISR) or a device driver requests a timestamp associated with the interrupt. Rather than send a request to the operating system to obtain a current value stored in the main time base counter, the processor requests the recorded timestamp from the IC. The IC identifies the stored timestamp associated with the interrupt and returns it to the processor.

Abstract translation: 一种用于保持精确中断时间戳的系统和方法。 半导体芯片包括具有多个中断源的接口的中断控制器（IC）。 响应于接收到中断，IC复制并记录存储在用于维持全局经过时间的主时基计数器中的值。 IC向对应的处理器发送中断指示。 中断服务程序（ISR）或设备驱动程序请求与中断相关联的时间戳。 处理器不是向操作系统发送请求以获得存储在主时基计数器中的当前值，而是从IC请求记录的时间戳。 IC识别与中断相关联的存储时间戳，并将其返回给处理器。

公开(公告)号：US12117320B2

公开(公告)日：2024-10-15

申请号：US17366459

申请日：2021-07-02

Applicant: Apple Inc.

Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal ,  Michael F. Culbert

IPC: G01D9/00 ,  A61G3/06 ,  B60P1/43 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/16

CPC classification number: G01D9/00 ,  A61G3/061 ,  B60P1/433 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/00 ,  Y02D30/50

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when a central processing unit (CPU) processor and a memory controller of the SOC are powered off. The component may include a sensor capture unit to capture audio samples from an audio detector circuit and write them to a memory of the component. A processor of the component may be configured to search the audio samples for a predetermined pattern during a time when the CPU processor and the memory controller are powered down. In some embodiments, based on the audio samples filling to a threshold level in the memory of the component and a lack of detection of the predetermined pattern, the component is configured to wake up the memory controller and a path to the memory controller in order to write the audio sample to a memory controlled by the memory controller.

公开(公告)号：US20220058292A1

公开(公告)日：2022-02-24

申请号：US17469591

申请日：2021-09-08

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, JR. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/14 ,  G06F21/78 ,  H04L9/08

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US11049503B2

公开(公告)日：2021-06-29

申请号：US16786127

申请日：2020-02-10

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/22 ,  G10L15/28 ,  G06F3/16 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/32 ,  G10L15/08 ,  G10L25/48

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

公开(公告)号：US10802968B2

公开(公告)日：2020-10-13

申请号：US14705506

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Harshavardhan Kaushikkar ,  Munetoshi Fukami ,  Gurjeet S. Saund ,  Manu Gulati ,  Shinye Shiu

IPC: G06F12/0815 ,  G06F12/0813 ,  G06F9/52

Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.