公开(公告)号：US08198677B2

公开(公告)日：2012-06-12

申请号：US12499778

申请日：2009-07-08

申请人： Peter H. Wilson ,  Steven Sapp

发明人： Peter H. Wilson ,  Steven Sapp

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/7835

摘要： MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias.

摘要翻译： 用于RF应用的MOSFET器件，其使用沟槽栅极代替横向MOSFET器件中常规使用的横向栅极。 沟槽栅为高频增益提供单通道，短通道。 本发明的实施例提供了在沟槽栅极中具有不对称氧化物的器件，以及降低栅极 - 漏极电容以提高RF性能的LDD区域。 对这些TG-LDMOS器件的改进包括将源极屏蔽导体放置在栅极下方并将两个栅极放置在沟槽栅极区域中。 这些通过降低栅极 - 漏极电容来提高器件的高频性能。 进一步的改进包括向LDD区域添加电荷平衡区域并添加源到衬底或漏极到衬底的通孔。

公开(公告)号：US20110163732A1

公开(公告)日：2011-07-07

申请号：US12845999

申请日：2010-07-29

申请人： Steven Sapp ,  Ashok Challa ,  Christopher B. Kocon

发明人： Steven Sapp ,  Ashok Challa ,  Christopher B. Kocon

IPC分类号： G05F1/618

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/7803

摘要： A synchronous buck converter includes a high-side switch and a low-side switch serially coupled to one another. The low-side switch includes a field effect transistor that comprises: a trench extending into a drift region of the field effect transistor; a shield electrode in a lower portion of the trench, wherein the shield electrode is insulated from the drift region by a shield dielectric; a gate electrode in the trench over the shield electrode, wherein the gate electrode is insulated from the shield electrode by an inter-electrode dielectric; source regions adjacent the trench; a source metal contacting the source regions; and a resistive element having one end contacting the shield electrode and another end contacting the source metal in the field effect transistor.

摘要翻译： 同步降压转换器包括彼此串联耦合的高侧开关和低侧开关。 低侧开关包括场效应晶体管，其包括：延伸到场效应晶体管的漂移区域的沟槽; 在所述沟槽的下部中的屏蔽电极，其中所述屏蔽电极通过屏蔽电介质与所述漂移区域绝缘; 在所述屏蔽电极上的沟槽中的栅电极，其中所述栅电极通过电极间电介质与所述屏蔽电极绝缘; 与沟槽相邻的源区; 源极金属与源极区域接触; 以及电阻元件，其一端接触屏蔽电极，另一端接触场效应晶体管中的源极金属。

公开(公告)号：US20100258855A1

公开(公告)日：2010-10-14

申请号：US12822008

申请日：2010-06-23

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

摘要翻译： 场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。 多个沟槽包括多个门控沟槽和多个非门控沟槽。 第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。 电介质材料填充每个门控沟槽和非门控沟槽的底部。 栅极电极设置在每个门控沟槽中。 第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

公开(公告)号：US20100038708A1

公开(公告)日：2010-02-18

申请号：US12582487

申请日：2009-10-20

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.

摘要翻译： 形成电荷平衡MOSFET的方法包括以下步骤。 提供了具有第一导电类型的上覆外延层的衬底。 形成延伸穿过外延层并终止在衬底内的栅极沟槽。 形成栅极沟槽的侧壁和底表面的屏蔽电介质。 在栅极沟槽中形成屏蔽电极。 栅极电介质层沿栅极沟槽的上侧壁形成。 栅电极形成在栅极沟槽中，使得栅电极延伸过去但与屏蔽电极绝缘。 形成延伸穿过外延层并终止于衬底内的深凹坑，使得深凹坑与栅沟槽横向间隔开。 深凹坑填充有第二导电类型的硅材料。

公开(公告)号：US07625799B2

公开(公告)日：2009-12-01

申请号：US12418949

申请日：2009-04-06

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L23/62

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.

摘要翻译： 提供了具有在半导体区域上延伸的外延层的半导体区域。 执行第一硅蚀刻以形成延伸到外延层内并在外延层内终止的上沟槽部分。 沿着上沟槽部分的侧壁以及与上沟槽部分相邻的台面区域，而不是沿着上沟槽部分的底表面延伸形成保护材料。 执行第二硅蚀刻以形成从上沟槽部分的底表面延伸穿过外延层并终止在半导体区域内的下沟槽部分，使得下沟槽部分比上沟槽部分窄。 执行第一导电类型的掺杂剂的双向成角度注入，以形成沿着下沟槽部分的侧壁的第一导电类型的硅区域，而保护材料阻挡注入掺杂剂进入上沟槽部分的侧壁 以及与上沟槽部分相邻的台面区域。

公开(公告)号：US20090261461A1

公开(公告)日：2009-10-22

申请号：US12104182

申请日：2008-04-16

申请人： Steven Sapp ,  Chung-Lin Wu ,  Maria Christina B. Estacio ,  Bigildis Dosdos ,  Hamza Yilmaz

发明人： Steven Sapp ,  Chung-Lin Wu ,  Maria Christina B. Estacio ,  Bigildis Dosdos ,  Hamza Yilmaz

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49562 ,  H01L23/49524 ,  H01L23/49548 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2924/206

摘要： Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ⅕ to about ½ the height of a lead finger, a width that is about ⅕ to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB). The lead intrusion allows out gassing during reflow of the bond material which may reduce voiding. The lead intrusion can also increase bond joint reliability by providing longer crack propagation length.

摘要翻译： 描述了包括在引线的边缘处包含铅侵入的多个引线指的半导体封装。 半导体封装包括连接到管芯焊盘并且电连接到多个引线指的集成电路芯片。 一个或多个引导指可以具有设置在引线指的外部暴露下表面上的引线侵入。 引线入侵可以具有引导指的高度的约1/5至约1/2的高度，宽度是引线指的宽度的大约1/5至大约1/2，并且深度约为1/4 到铅笔的外部暴露的下表面的长度的约3/4。 引线入侵增加了引线接触诸如焊料的接合材料的引线区域，因此增加了半导体封装与引线指连接的外表面（即PCB）之间的接合强度。 铅侵入允许在回流焊接材料期间放气，这可能减少空隙。 铅侵入也可以通过提供更长的裂纹扩展长度来增加接合点的可靠性。

公开(公告)号：US20090191678A1

公开(公告)日：2009-07-30

申请号：US12418949

申请日：2009-04-06

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/334

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.

摘要翻译： 提供了具有在半导体区域上延伸的外延层的半导体区域。 执行第一硅蚀刻以形成延伸到外延层内并在外延层内终止的上沟槽部分。 沿着上沟槽部分的侧壁以及与上沟槽部分相邻的台面区域，而不是沿着上沟槽部分的底表面延伸形成保护材料。 执行第二硅蚀刻以形成从上沟槽部分的底表面延伸穿过外延层并终止在半导体区域内的下沟槽部分，使得下沟槽部分比上沟槽部分窄。 执行第一导电类型的掺杂剂的双向成角度注入以在下沟槽部分的侧壁形成第一导电类型的硅区域，而保护材料阻挡注入掺杂剂进入上沟槽部分的侧壁 以及与上沟槽部分相邻的台面区域。

公开(公告)号：US07291894B2

公开(公告)日：2007-11-06

申请号：US10931887

申请日：2004-08-31

申请人： Steven Sapp ,  Peter H. Wilson

发明人： Steven Sapp ,  Peter H. Wilson

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/405 ,  H01L29/407 ,  H01L29/7802 ,  H01L29/7813

摘要： In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.

摘要翻译： 根据本发明的实施例，MOSFET包括在第一半导体区域中横向间隔开的至少两个绝缘填充沟槽区域，以在其间形成漂移区域，以及至少一个电阻元件沿着每个 两个绝缘填充沟槽区域。 调整每个绝缘填充沟槽区域的宽度与漂移区域的宽度的比率，使得MOSFET的输出电容最小化。

公开(公告)号：US20070082441A1

公开(公告)日：2007-04-12

申请号：US11551992

申请日：2006-10-23

申请人： Nathan Kraft ,  Ashok Challa ,  Steven Sapp ,  Hamza Yilmaz ,  Daniel Calafut ,  Dean Probst ,  Rodney Ridley ,  Thomas Grebs ,  Christopher Kocon ,  Joseph Yedinak ,  Gary Dolny

发明人： Nathan Kraft ,  Ashok Challa ,  Steven Sapp ,  Hamza Yilmaz ,  Daniel Calafut ,  Dean Probst ,  Rodney Ridley ,  Thomas Grebs ,  Christopher Kocon ,  Joseph Yedinak ,  Gary Dolny

IPC分类号： H01L21/8242

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： A field effect transistor is formed as follows. Trenches are formed in a semiconductor region of a first conductivity type. Each trench is partially filled with one or more materials. A dual-pass angled implant is carried out to implant dopants of a second conductivity type into the semiconductor region through an upper surface of the semiconductor region and through upper trench sidewalls not covered by the one or more material. A high temperature process is carried out to drive the implanted dopants deeper into the mesa region thereby forming body regions of the second conductivity type between adjacent trenches. Source regions of the first conductivity type are then formed in each body region.

摘要翻译： 场效应晶体管如下形成。 沟槽形成在第一导电类型的半导体区域中。 每个沟槽部分地填充有一种或多种材料。 执行双通角度注入以通过半导体区域的上表面和不被一种或多种材料覆盖的上沟槽侧壁将第二导电类型的掺杂剂注入半导体区域。 进行高温处理以将注入的掺杂剂更深地驱动到台面区域中，从而在相邻的沟槽之间形成第二导电类型的体区。 然后在每个身体区域中形成第一导电类型的源区域。

公开(公告)号：US20060273386A1

公开(公告)日：2006-12-07

申请号：US11441386

申请日：2006-05-24

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Kocon ,  Steven Sapp ,  Dean Probst ,  Nathan Kraft ,  Thomas Grebs ,  Rodney Ridley ,  Gary Dolny ,  Bruce Marchant ,  Joseph Yedinak

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Christopher Kocon ,  Steven Sapp ,  Dean Probst ,  Nathan Kraft ,  Thomas Grebs ,  Rodney Ridley ,  Gary Dolny ,  Bruce Marchant ,  Joseph Yedinak

IPC分类号： H01L29/94

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.

摘要翻译： 场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。 栅极沟槽延伸穿过身体区域并终止在半导体区域内。 至少一个导电屏蔽电极设置在栅极沟槽中。 栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。 屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。 栅极电介质层使栅电极与体区绝缘。 屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。