公开(公告)号：US20090261461A1

公开(公告)日：2009-10-22

申请号：US12104182

申请日：2008-04-16

申请人： Steven Sapp ,  Chung-Lin Wu ,  Maria Christina B. Estacio ,  Bigildis Dosdos ,  Hamza Yilmaz

发明人： Steven Sapp ,  Chung-Lin Wu ,  Maria Christina B. Estacio ,  Bigildis Dosdos ,  Hamza Yilmaz

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49562 ,  H01L23/49524 ,  H01L23/49548 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/37147 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2924/206

摘要： Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ⅕ to about ½ the height of a lead finger, a width that is about ⅕ to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB). The lead intrusion allows out gassing during reflow of the bond material which may reduce voiding. The lead intrusion can also increase bond joint reliability by providing longer crack propagation length.

摘要翻译： 描述了包括在引线的边缘处包含铅侵入的多个引线指的半导体封装。 半导体封装包括连接到管芯焊盘并且电连接到多个引线指的集成电路芯片。 一个或多个引导指可以具有设置在引线指的外部暴露下表面上的引线侵入。 引线入侵可以具有引导指的高度的约1/5至约1/2的高度，宽度是引线指的宽度的大约1/5至大约1/2，并且深度约为1/4 到铅笔的外部暴露的下表面的长度的约3/4。 引线入侵增加了引线接触诸如焊料的接合材料的引线区域，因此增加了半导体封装与引线指连接的外表面（即PCB）之间的接合强度。 铅侵入允许在回流焊接材料期间放气，这可能减少空隙。 铅侵入也可以通过提供更长的裂纹扩展长度来增加接合点的可靠性。

公开(公告)号：US07635635B2

公开(公告)日：2009-12-22

申请号：US11400731

申请日：2006-04-06

申请人： Hamza Yilmaz ,  Qi Wang ,  Minhua Li ,  Chung-Lin Wu

发明人： Hamza Yilmaz ,  Qi Wang ,  Minhua Li ,  Chung-Lin Wu

IPC分类号： H01L21/46

CPC分类号： H01L21/76251 ,  H01L21/6835 ,  H01L24/28 ,  H01L29/78603 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665

摘要： A method of bonding a semiconductor substrate to a metal substrate is disclosed. In some embodiments the method includes forming a semiconductor device in a semiconductor substrate, the semiconductor device comprising a first surface. The method further includes obtaining a metal substrate. The metal substrate is bonded to the first surface of the semiconductor device, wherein at least a portion of the metal substrate forms an electrical terminal for the semiconductor device.

摘要翻译： 公开了将半导体衬底接合到金属衬底的方法。 在一些实施例中，该方法包括在半导体衬底中形成半导体器件，该半导体器件包括第一表面。 该方法还包括获得金属基底。 金属基板结合到半导体器件的第一表面，其中金属基板的至少一部分形成用于半导体器件的电端子。

公开(公告)号：US20070238263A1

公开(公告)日：2007-10-11

申请号：US11400731

申请日：2006-04-06

申请人： Hamza Yilmaz ,  Qi Wang ,  Minhua Li ,  Chung-Lin Wu

发明人： Hamza Yilmaz ,  Qi Wang ,  Minhua Li ,  Chung-Lin Wu

IPC分类号： H01L21/30

CPC分类号： H01L21/76251 ,  H01L21/6835 ,  H01L24/28 ,  H01L29/78603 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665

摘要： A method of bonding a semiconductor substrate to a metal substrate is disclosed. In some embodiments the method includes forming a semiconductor device in a semiconductor substrate, the semiconductor device comprising a first surface. The method further includes obtaining a metal substrate. The metal substrate is bonded to the first surface of the semiconductor device, wherein at least a portion of the metal substrate forms an electrical terminal for the semiconductor device.

摘要翻译： 公开了将半导体衬底接合到金属衬底的方法。 在一些实施例中，该方法包括在半导体衬底中形成半导体器件，该半导体器件包括第一表面。 该方法还包括获得金属基底。 金属基板结合到半导体器件的第一表面，其中金属基板的至少一部分形成用于半导体器件的电端子。

公开(公告)号：US07393749B2

公开(公告)日：2008-07-01

申请号：US11450903

申请日：2006-06-08

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L23/62

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A field effect transistor is formed as follows. A semiconductor region of a first conductivity type with an epitaxial layer of a second conductivity extending over the semiconductor region is provided. A trench extending through the epitaxial layer and terminating in the semiconductor region is formed. A two-pass angled implant of dopants of the first conductivity type is carried out to thereby form a region of first conductivity type along the trench sidewalls. A threshold voltage adjust implant of dopants of the second conductivity type is carried out to thereby convert a conductivity type of a portion of the region of first conductivity type extending along upper sidewalls of the trench to the second conductivity type. Source regions of the first conductivity type flanking each side of the trench are formed.

摘要翻译： 场效应晶体管如下形成。 提供了具有在半导体区域上延伸的具有第二导电性的外延层的第一导电类型的半导体区域。 形成延伸穿过外延层并终止在半导体区域中的沟槽。 执行第一导电类型的掺杂剂的双向成角度注入，从而沿着沟槽侧壁形成第一导电类型的区域。 执行阈值电压调整第二导电类型的掺杂剂的注入，从而将沿沟槽的上侧壁延伸的第一导电类型区域的一部分的导电类型转换为第二导电类型。 形成沟槽每一侧的第一导电类型的源区。

公开(公告)号：US20080087963A1

公开(公告)日：2008-04-17

申请号：US11865191

申请日：2007-10-01

申请人： Daniel Calafut ,  Hamza Yilmaz ,  Steven Sapp

发明人： Daniel Calafut ,  Hamza Yilmaz ,  Steven Sapp

IPC分类号： H01L27/06

CPC分类号： H01L29/866 ,  H01L27/0255 ,  H01L29/7808 ,  H01L2924/0002 ,  H03K17/08122 ,  H03K17/0822 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection network for power MOSFETs includes parallel branches, containing polysilicon zener diodes and resistors, used for protecting the gate from rupture caused by high voltages caused by ESD. The branches may have the same or independent paths for voltage to travel across from the gate region into the semiconductor substrate. Specifically, the secondary branch has a higher breakdown voltage than the primary branch so that the voltage is shared across the two branches of the protection network. The ESD protection network of the device provides a more effective design without increasing the space used on the die. The ESD protection network can also be used with other active and passive devices such as thyristors, insulated-gate bipolar transistors, and bipolar junction transistors.

摘要翻译： 用于功率MOSFET的静电放电（ESD）保护网络包括并联支路，其包含多晶硅齐纳二极管和电阻器，用于保护栅极免受由ESD引起的高压引起的破坏。 分支可以具有相同或独立的路径，用于电压跨越栅极区域进入半导体衬底。 具体地，次级分支具有比主分支更高的击穿电压，使得电压在保护网络的两个分支上共享。 器件的ESD保护网络提供了更有效的设计，而不增加芯片上使用的空间。 ESD保护网络还可以与其他有源和无源器件如晶闸管，绝缘栅双极晶体管和双极结型晶体管一起使用。

公开(公告)号：US20060267090A1

公开(公告)日：2006-11-30

申请号：US11398467

申请日：2006-04-04

申请人： Steven Sapp ,  Hamza Yilmaz ,  Christopher Rexer ,  Daniel Calafut

发明人： Steven Sapp ,  Hamza Yilmaz ,  Christopher Rexer ,  Daniel Calafut

IPC分类号： H01L29/76

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： A monolithically integrated field effect transistor and Schottky diode includes gate trenches extending into a semiconductor region. Source regions having a substantially triangular shape flank each side of the gate trenches. A contact opening extends into the semiconductor region between adjacent gate trenches. A conductor layer fills the contact opening to electrically contact: (a) the source regions along at least a portion of a slanted sidewall of each source region, and (b) the semiconductor region along a bottom portion of the contact opening, wherein the conductor layer forms a Schottky contact with the semiconductor region.

摘要翻译： 单片集成场效应晶体管和肖特基二极管包括延伸到半导体区域的栅极沟槽。 源极区域具有位于栅极沟槽的每一侧的大致三角形形状。 接触开口延伸到相邻栅极沟槽之间的半导体区域中。 导体层填充接触开口以电接触：（a）源区域沿着每个源极区域的倾斜侧壁的至少一部分，以及（b）沿接触开口底部的半导体区域，其中导体 层与半导体区形成肖特基接触。

公开(公告)号：US07768075B2

公开(公告)日：2010-08-03

申请号：US11400729

申请日：2006-04-06

申请人： Hamza Yilmaz ,  Steven Sapp ,  Qi Wang ,  Minhua Li ,  James J. Murphy ,  John Robert Diroll

发明人： Hamza Yilmaz ,  Steven Sapp ,  Qi Wang ,  Minhua Li ,  James J. Murphy ,  John Robert Diroll

IPC分类号： H01L27/088

CPC分类号： H01L23/3114 ,  H01L23/481 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/072 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06102 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

摘要翻译： 公开了一种半导体管芯封装。 半导体管芯封装包括金属基板和半导体管芯，其包括第一表面，第一表面包括第一电端子，第二表面，包括第二电端子和至少一个孔。 金属基板附接到第二表面。 多个导电结构在半导体管芯上，并且包括设置在该至少一个孔中的至少一个导电结构。 其他导电结构可以设置在半导体管芯的第一表面上。

公开(公告)号：US07767524B2

公开(公告)日：2010-08-03

申请号：US12582487

申请日：2009-10-20

申请人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

发明人： Hamza Yilmaz ,  Daniel Calafut ,  Steven Sapp ,  Nathan Kraft ,  Ashok Challa

IPC分类号： H01L21/336 ,  H01L23/62

CPC分类号： H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.

摘要翻译： 形成电荷平衡MOSFET的方法包括以下步骤。 提供了具有第一导电类型的上覆外延层的衬底。 形成延伸穿过外延层并终止在衬底内的栅极沟槽。 形成栅极沟槽的侧壁和底表面的屏蔽电介质。 在栅极沟槽中形成屏蔽电极。 栅极电介质层沿栅极沟槽的上侧壁形成。 栅电极形成在栅极沟槽中，使得栅电极延伸过去但与屏蔽电极绝缘。 形成延伸穿过外延层并终止于衬底内的深凹坑，使得深凹坑与栅沟槽横向间隔开。 深凹坑填充有第二导电类型的硅材料。

公开(公告)号：US20070235886A1

公开(公告)日：2007-10-11

申请号：US11400729

申请日：2006-04-06

申请人： Hamza Yilmaz ,  Steven Sapp ,  Qi Wang ,  Minhua Li ,  James Murphy ,  John Diroll

发明人： Hamza Yilmaz ,  Steven Sapp ,  Qi Wang ,  Minhua Li ,  James Murphy ,  John Diroll

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/481 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/072 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06102 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1411 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

摘要翻译： 公开了一种半导体管芯封装。 半导体管芯封装包括金属基板和半导体管芯，其包括第一表面，第一表面包括第一电端子，第二表面，包括第二电端子和至少一个孔。 金属基板附接到第二表面。 多个导电结构在半导体管芯上，并且包括设置在该至少一个孔中的至少一个导电结构。 其他导电结构可以设置在半导体管芯的第一表面上。

公开(公告)号：US08680611B2

公开(公告)日：2014-03-25

申请号：US13600184

申请日：2012-08-30

申请人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

发明人： Christopher Boguslaw Kocon ,  Steven Sapp ,  Paul Thorup ,  Dean Probst ,  Robert Herrick ,  Becky Losee ,  Hamza Yilmaz ,  Christopher Lawrence Rexer ,  Daniel Calafut

IPC分类号： H01L29/76

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L2924/13091

摘要： In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

摘要翻译： 根据实施例，结构可以包括单片集成沟槽场效应晶体管（FET）和肖特基二极管。 该结构可以包括延伸到半导体区域的第一栅极沟槽，延伸到半导体区域中的第二栅极沟槽和在第一栅极沟槽的侧面的源极区域。 源极区域可以具有基本上三角形的形状，以及延伸到第一栅极沟槽和第二栅极沟槽之间的半导体区域中的接触开口。 该结构可以包括设置在接触开口中的导体层，以沿着源极区域的倾斜侧壁的至少一部分以及沿接触开口的底部部分的半导体区域电接触源极区域。 导体层可与半导体区形成肖特基接触。