公开(公告)号：US20120073208A1

公开(公告)日：2012-03-29

申请号：US13322635

申请日：2010-05-24

Applicant: Chul Lee

Inventor： Chul Lee

IPC: E05B47/00 ,  E05C1/12

CPC classification number: E05F15/655 ,  E05F15/652 ,  E05Y2201/22 ,  E05Y2201/232 ,  E05Y2201/638 ,  E05Y2201/64 ,  E05Y2201/702 ,  E05Y2800/116 ,  E05Y2800/21 ,  E05Y2900/51 ,  Y10T292/1016

Abstract: The invention relates to an electric door-locking system to be applied to at least one electric door body that is movable in a sliding manner, and includes forwardly and reversely rotatable screws disposed side by side along a direction in which the electric door body slides at the side of a door frame; a cam assembly provided at a predetermined position of the screws to perform a locking function and an unlocking function; and a sliding unit provided with a locking roller resiliently biased in a direction toward the cam assembly and engaging with the cam assembly to perform the locking function, one end of the sliding unit being rotatably connected to the screw and the other end of the sliding unit being connected to the electric door body.

Abstract translation: 本发明涉及一种电动门锁系统，其应用于至少一个可滑动移动的电动门体，并且包括沿着电动门体滑动方向并排设置的向前和反向旋转的螺钉 门框的一侧; 凸轮组件，其设置在所述螺钉的预定位置处以执行锁定功能和解锁功能; 以及滑动单元，其具有沿朝向凸轮组件的方向弹性偏压并与凸轮组件接合以执行锁定功能的锁定辊，滑动单元的一端可旋转地连接到螺钉，滑动单元的另一端 连接到电动门体。

公开(公告)号：US20110171800A1

公开(公告)日：2011-07-14

申请号：US12944870

申请日：2010-11-12

Applicant: Bongsoo Kim ,  Chul Lee ,  Deoksung Hwang ,  Sang-Bin Ahn

Inventor： Bongsoo Kim ,  Chul Lee ,  Deoksung Hwang ,  Sang-Bin Ahn

IPC: H01L21/336

CPC classification number: H01L29/4236 ,  H01L21/823437 ,  H01L29/66621 ,  H01L29/78

Abstract: A polycrystalline semiconductor layer is formed on a cell active region and a peripheral active region of a substrate. A buried gate electrode is formed in the substrate in the cell active region at a level below the polycrystalline semiconductor layer after forming the polycrystalline semiconductor layer. A gate electrode is formed on the substrate in the peripheral active region from the polysilicon semiconductor layer after forming the buried gate electrode.

Abstract translation: 多晶半导体层形成在基板的单元有源区和周边有源区上。 在形成多晶半导体层之后，在多晶半导体层下方的电池有源区的基板中形成掩埋栅电极。 在形成掩埋栅电极之后，在多晶硅半导体层的外围有源区的基板上形成栅电极。

公开(公告)号：US07919378B2

公开(公告)日：2011-04-05

申请号：US12397176

申请日：2009-03-03

Applicant: Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

Inventor： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

Abstract translation: 根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。 活性结构包括在源极/漏极区域下形成阻挡区的沟槽。 栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。 可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

公开(公告)号：US20090189217A1

公开(公告)日：2009-07-30

申请号：US12418879

申请日：2009-04-06

Applicant: Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

Inventor： Jae-man Yoon ,  Dong-gun Park ,  Choong-ho Lee ,  Moon-suk Yi ,  Chul Lee

IPC: H01L29/78

CPC classification number: H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/66666

Abstract: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

Abstract translation: 半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。 相邻的围绕电极围绕其中的一个柱。 第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。 掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极 地区。

公开(公告)号：US20090186471A1

公开(公告)日：2009-07-23

申请号：US12321335

申请日：2009-01-20

Applicant: Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

Inventor： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

IPC: H01L21/426 ,  H01L21/04

CPC classification number: H01L21/823814 ,  H01L21/823425 ,  H01L21/82385

Abstract: A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

Abstract translation: 制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法包括制备包括单元阵列区域中的单元有源区和外围电路区中的外围有源区的基板。 单元栅极图案和外围栅极图案可以形成在单元有源区域和外围有源区域上。 可以在电池活性区域中形成第一电池杂质区域。 可以形成第一绝缘层和牺牲绝缘层以围绕电池栅极图案和外围栅极图案。 电池导电焊盘可以形成在第一绝缘层中以电连接第一电池杂质区。 牺牲绝缘层可以与外围栅极图案相邻地去除。 第一和第二外围杂质区域可以顺序地形成在与外围栅极图案相邻的外围有源区域中。

公开(公告)号：US20080185641A1

公开(公告)日：2008-08-07

申请号：US12068179

申请日：2008-02-04

Applicant: Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

Inventor： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

Abstract: A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

Abstract translation: 提供凹陷晶体管及其制造方法。 凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。 衬底可以包括建立衬底的有源区和场区的隔离层。 衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。 有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。 栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。 源/漏区可以与有源区和栅电极相邻形成。

公开(公告)号：US20070190725A1

公开(公告)日：2007-08-16

申请号：US11740525

申请日：2007-04-26

Applicant: Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

Inventor： Tae-yong Kim ,  Choong-ho Lee ,  Chul Lee ,  Eun-suk Cho ,  Suk-kang Sung ,  Hye-jin Cho

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11568

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.

Abstract translation: 半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质 所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触 以及与第一线成直角形成并覆盖沟道区的字线。

公开(公告)号：US20070134884A1

公开(公告)日：2007-06-14

申请号：US11488584

申请日：2006-07-18

Applicant: Keun-Nam Kim ,  Chul Lee ,  Eun-Suk Cho

Inventor： Keun-Nam Kim ,  Chul Lee ,  Eun-Suk Cho

IPC: H01L21/76 ,  H01L29/00 ,  H01L21/4763

CPC classification number: H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7851

Abstract: An isolation method of defining active fins, a method of fabricating a semiconductor device using the same, and a semiconductor device fabricated thereby are provided. The method of fabricating a semiconductor device includes: preparing a semiconductor substrate; and forming a plurality of active fins having major and minor axes and two-dimensionally arrayed on the semiconductor substrate in directions of the major and minor axes. A liner pattern is formed on lower sidewalls of the active fins. An isolation layer is formed on the semiconductor substrate having the liner pattern, and the isolation layer exposes top surfaces of the active fins and a part of the active fins' sidewalls substantially parallel to the major axis. Parallel gate lines are formed to cover the top surfaces and the exposed sidewalls of the active fins, cross over the active fins, and run on the isolation layer.

Abstract translation: 提供了限定有源散热片的隔离方法，制造使用其的半导体器件的方法以及由此制造的半导体器件。 制造半导体器件的方法包括：制备半导体衬底; 并且在所述主轴和短轴的方向上形成具有主轴和短轴的多个有源散热片，并且二维排列在所述半导体基板上。 衬垫图案形成在活动鳍片的下侧壁上。 在具有衬垫图案的半导体衬底上形成隔离层，并且隔离层暴露活性鳍片的顶表面和基本上平行于长轴的活性鳍片侧壁的一部分。 形成平行栅极线以覆盖活性鳍片的顶表面和暴露的侧壁，跨过活性鳍片并且在隔离层上运行。

公开(公告)号：US20070010699A1

公开(公告)日：2007-01-11

申请号：US11426847

申请日：2006-06-27

Applicant: Sun Choi ,  Yong Kim ,  Deuk Park ,  Suk Kim ,  Il Yang ,  Hee Kim ,  Yong Park ,  Chul Lee ,  Won Choi ,  Kwang Ko ,  Na Kang

Inventor： Sun Choi ,  Yong Kim ,  Deuk Park ,  Suk Kim ,  Il Yang ,  Hee Kim ,  Yong Park ,  Chul Lee ,  Won Choi ,  Kwang Ko ,  Na Kang

IPC: C07C4/02

CPC classification number: C07C4/06 ,  C10G2400/20 ,  C07C11/02

Abstract: Disclosed is a process for producing light olefins from hydrocarbon feedstock. The process is characterized in that a porous molecular sieve catalyst consisting of a product obtained by evaporating water from a raw material mixture comprising a molecular sieve with a framework of Si—OH—Al— groups, a water-insoluble metal salt, and a phosphate compound, is used to produce light olefins, particularly ethylene and propylene, from hydrocarbon, while maintaining excellent selectivity to light olefins. According to the process, by the use of a specific catalyst with hydrothermal stability, light olefins can be selectively produced in high yield with high selectivity from hydrocarbon feedstock, particularly full-range naphtha. In particular, the process can maintain higher cracking activity than the reaction temperature required in the prior thermal cracking process for the production of light olefins, and thus, can produce light olefins with high selectivity and conversion from hydrocarbon feedstock.

Abstract translation: 公开了一种从烃原料生产轻质烯烃的方法。 该方法的特征在于，由通过从包含具有Si-OH-Al-基团的骨架的分子筛，水不溶性金属盐和磷酸盐的原料混合物蒸发水而获得的产物的多孔分子筛催化剂 化合物，用于从烃生产轻质烯烃，特别是乙烯和丙烯，同时保持对轻质烯烃的优异选择性。 根据该方法，通过使用具有水热稳定性的特定催化剂，可以从烃原料，特别是全范围石脑油以高选择性高选择性地制备轻质烯烃。 特别地，该方法可以保持比用于生产轻质烯烃的现有热裂解方法中所需的反应温度更高的裂化活性，因此可以从烃原料生产具有高选择性和转化率的轻质烯烃。

公开(公告)号：US20060133440A1

公开(公告)日：2006-06-22

申请号：US11170813

申请日：2005-06-30

Applicant: Ki Kim ,  Chul Lee ,  Dong Lee ,  Jung Song ,  Eun Sim ,  Sung Kim ,  Yong Baek

Inventor： Ki Kim ,  Chul Lee ,  Dong Lee ,  Jung Song ,  Eun Sim ,  Sung Kim ,  Yong Baek

IPC: H01S5/20

CPC classification number: H01S5/3434 ,  B82Y20/00 ,  H01L33/06 ,  H01S5/2004 ,  H01S5/2009 ,  H01S5/3403 ,  H01S5/34373

Abstract: Provided is an optical semiconductor device including: an active layer having at least one quantum well layer and at least one barrier layer; a clad layer formed adjacent to the active layer; and a tunneling barrier layer formed between the active layer and the clad layer to be connected to the quantum well layer and formed of a material having a band-gap energy larger than the barrier layer, whereby it is possible to improve the drive characteristics at a high temperature and a high drive current by increasing a confinement effect of carriers such as electrons and holes in the active layer.

Abstract translation: 本发明提供一种光半导体装置，包括：有源层，具有至少一个量子阱层和至少一个阻挡层; 与活性层相邻形成的覆层; 以及形成在有源层和包层之间的隧道势垒层，以与量子阱层连接并由具有比阻挡层大的带隙能量的材料形成，从而可以提高在 通过增加载体如电子和空穴在活性层中的约束效应，可以提高高温和高驱动电流。