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81 条记录 (耗时 0.027 秒)

    Phase lock loop (PLL) apparatus and method
    61.
    发明授权
    Phase lock loop (PLL) apparatus and method 有权

    公开(公告)号：US06424192B1

    公开(公告)日：2002-07-23

    申请号：US09709311

    申请日：2000-11-13

    申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

    发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

    IPC分类号： H03L706

    CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/40

    摘要： A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

    Gm-C tuning circuit with filter configuration
    62.
    发明授权
    Gm-C tuning circuit with filter configuration 有权

    公开(公告)号：US06404277B1

    公开(公告)日：2002-06-11

    申请号：US09709310

    申请日：2000-11-13

    申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

    发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

    IPC分类号： H03K501

    CPC分类号： H04B1/28 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/40 ,  H04B1/403

    摘要： A tuning circuit for an RF communications system and method includes a master block that outputs a control signal to a slave block. The master block can include a first filter having a high pass filter and a low pass filter that each receive the control signal, a first rectifier coupled to the high pass filter, a second rectifier coupled to the low pass filter, and a converter coupled to the first and second rectifiers that outputs the control signal. The first filter is preferably a gm-C poly-phase filter. Output signals of the gm-C poly-phase filter include high and low pass filtering signals resulting from similarly configured circuits so that the output signals have the same electrical characteristics, which results in an increased accuracy, for example, in a cut-off frequency.

    System for Distributing Clocks
    63.
    发明授权
    System for Distributing Clocks 失效
    分配时钟系统

    公开(公告)号：US06211714B1

    公开(公告)日：2001-04-03

    申请号：US09013679

    申请日：1998-01-26

    申请人： Deog-Kyoon Jeong

    发明人： Deog-Kyoon Jeong

    IPC分类号： G06F104

    CPC分类号： H04L7/0338 ,  H03K19/018592 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/0996 ,  H03M9/00 ,  H04J3/047 ,  H04L5/1423 ,  H04L7/0008 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/085

    摘要： A system for converting between parallel data and serial data is described. In the system, individual bits of the parallel data are latched into individual registers. Each register is coupled to a corresponding AND gate which is also connected to receive phased clock signals. The output terminals of the AND gates are connected to an OR gate. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

    摘要翻译： 描述用于在并行数据和串行数据之间转换的系统。 在系统中，并行数据的各个位被锁存到各个寄存器中。 每个寄存器耦合到相应的与门，该门也被连接以接收相位时钟信号。 与门的输出端连接到或门。 使用系统，使用适当的相位时钟，并行数据被转换为串行数据。

    Voltage-controlled oscillator resistant to supply voltage noise
    64.
    发明授权
    Voltage-controlled oscillator resistant to supply voltage noise 失效
    电压控制振荡器可抵抗电源电压噪声

    公开(公告)号：US5955929A

    公开(公告)日：1999-09-21

    申请号：US920336

    申请日：1997-08-27

    申请人： Yongsam Moon ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Deog-Kyoon Jeong

    IPC分类号： H03K3/013 ,  H03K3/0231 ,  H03K3/03 ,  H03B5/04 ,  H03B5/24

    CPC分类号： H03K3/0322 ,  H03K3/013 ,  H03K3/0231 ,  H03K3/03

    摘要： A voltage-controlled oscillator (VCO) generates an oscillating signal that is substantially resistant to noise fluctuations in the supply voltage. The VCO is a delay-based VCO which preferably includes a compensation circuit for each delay cell and a noise-immune reference current generator for providing a noise-immune bias current to the conditioning circuit of the VCO. The compensation circuit preferably adjusts the capacitance of the delay cell to compensate for the variations in current caused by the supply noise. The noise-immune reference current generator preferably utilizes a configuration of transistors which maintains through at least one transistor a substantially constant current which is used to bias the conditioning circuit.

    摘要翻译： 压控振荡器（VCO）产生基本上抵抗电源电压中的噪声波动的振荡信号。 VCO是基于延迟的VCO，其优选地包括用于每个延迟单元的补偿电路和用于向VCO的调理电路提供无噪声免疫偏置电流的无噪声免疫参考电流发生器。 补偿电路优选地调整延迟单元的电容以补偿由电源噪声引起的电流变化。 噪声免疫参考电流发生器优选地利用晶体管的配置，晶体管通过至少一个晶体管保持用于偏置调理电路的基本上恒定的电流。

    Method for generating digital communication system clock signals & circuitry for performing that method
    67.
    发明授权
    Method for generating digital communication system clock signals & circuitry for performing that method 失效
    用于产生用于执行该方法的数字通信系统时钟信号和电路的方法

    公开(公告)号：US5574756A

    公开(公告)日：1996-11-12

    申请号：US332561

    申请日：1994-10-31

    申请人： Deog-Kyoon Jeong

    发明人： Deog-Kyoon Jeong

    IPC分类号： H04L7/04 ,  H03L7/081 ,  H03L7/085 ,  H04L7/033 ,  H03D3/24

    CPC分类号： H03L7/085 ,  H03L7/0812 ,  H04L7/0337

    摘要： A clock generating circuit generates 2n clocks (where n is a positive integer number) each having 1/2n frequency of a maximum baud rate of data bit-stream input and a phase difference of .pi./n between successive phases thereof, and simultaneously shifts the phases on the clocks ahead or behind until the phases between the clocks and corresponding data bits of the data bit-stream input are locked in quadrature, by comparing the phase of the clock with those of data bit-stream input and adjusting the phases of the clocks.

    摘要翻译： 时钟发生电路产生2n个数据位流输入的最大波特率的+ E，fra 1/2 + EE n个频率的2n个时钟（n为正整数），连续的 并且同时在前面或后面的时钟上移动相位，直到通过将时钟的相位与数据比特流的相位相比较来将数据比特流输入的时钟和相应数据比特之间的相位锁定在正交上 输入和调整时钟的相位。

    Level-down shifter
    68.
    发明授权
    Level-down shifter 有权
    降档移位器

    公开(公告)号：US08829969B2

    公开(公告)日：2014-09-09

    申请号：US13357654

    申请日：2012-01-25

    申请人： Moon-Sang Hwang ,  Won-Jun Choe ,  Hyun-Chang Kim ,  Deog-Kyoon Jeong

    发明人： Moon-Sang Hwang ,  Won-Jun Choe ,  Hyun-Chang Kim ,  Deog-Kyoon Jeong

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018528

    摘要： A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage.

    摘要翻译： 电平降低移位器包括：第一电压和第一节点之间的第一负载装置; 在所述第一电压和第二节点之间的第二负载装置; 在所述第一节点和第三节点之间的第一输入装置，接收参考电压信号，以及基于所述参考电压信号调整所述第一节点的第一节点电压; 在所述第二节点和所述第三节点之间的第二输入设备，接收输入信号，以及基于所述输入信号调整所述第二节点的第二节点电压; 以及第二电压和第三节点之间的电流源，接收第二节点的第二节点电压，以及基于第二节点的第二节点电压调整第三节点的第三节点电压和偏置电流，其中， 输入信号的电平高于第一电压。

    COARSE LOCK DETECTOR
    70.
    发明申请
    COARSE LOCK DETECTOR 有权
    听力锁定检测器

    公开(公告)号：US20120212264A1

    公开(公告)日：2012-08-23

    申请号：US13398532

    申请日：2012-02-16

    申请人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

    发明人： Moon-Sang Hwang ,  Won-Jun Choe ,  Han-Kyu Chi ,  Deog-Kyoon Jeong

    IPC分类号： H03L7/00

    CPC分类号： H03L7/095 ,  H03L7/0812 ,  H03L7/101

    摘要： A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.

    摘要翻译： 公开了一种用于延迟锁定环（DLL）的粗略锁定检测器。 粗锁检测器包括多个检测单元。 每个检测单元接收延迟时钟相位和先前检测单元的输出作为输入。 为了增加先前检测单元的输出的时间传播，检测单元被分组排列，使得来自先前检测单元的输出是由多于一个先前检测单元的检测单元生成的。