公开(公告)号：US12112067B2

公开(公告)日：2024-10-08

申请号：US17884040

申请日：2022-08-09

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Iftekhar Rahman ,  Pedro Sanchez

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0673

Abstract: The present disclosure is drawn to, among other things, a method for programming a memory device comprising a plurality of memory arrays. The method may include receiving a command to program one or more of the plurality of memory arrays and programming the one or more of the plurality of memory arrays based on the command. The method may optionally include erasing the one or more of the plurality of memory arrays prior to the programming.

公开(公告)号：US11757451B2

公开(公告)日：2023-09-12

申请号：US17652905

申请日：2022-02-28

Applicant: Everspin Technologies, Inc.

Inventor： Dimitri Houssameddine ,  Syed M. Alam ,  Sanjeev Aggarwal

IPC: H03K19/1776 ,  G11C11/16 ,  G11C13/00 ,  H03K19/17784 ,  H03K19/17724 ,  G06F21/78

CPC classification number: H03K19/1776 ,  G11C11/1675 ,  G11C13/0069 ,  H03K19/17724 ,  H03K19/17784 ,  G06F21/78

Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.

公开(公告)号：US10608671B2

公开(公告)日：2020-03-31

申请号：US16288664

申请日：2019-02-28

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10

Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction is performed by the memory device on each of the ECC words associated with a page, and a second level of error correction is performed on the data output by each of the input/output pads, during a particular period of time. Each of the one or more input/output pads of the memory device is configured to provide only one bit of data per ECC word to an external source during an access from the external source.

公开(公告)号：US10304511B1

公开(公告)日：2019-05-28

申请号：US15959669

申请日：2018-04-23

Applicant: Everspin Technologies Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang ,  Thomas Andre

IPC: G11C11/16 ,  H03K5/1534 ,  H03K5/00

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a first memory cell, a first clock-generating circuit, and a second clock-generating circuit. The first clock-generating circuit is configured to provide a first output signal and a second output signal. The second clock-generating circuit is configured to provide a third output signal and a fourth output signal. The first output signal, the second output signal, the third output signal, and the fourth output signal are configured for controlling access operations for the first memory cell.

公开(公告)号：US10268591B2

公开(公告)日：2019-04-23

申请号：US15986167

申请日：2018-05-22

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian ,  Javed S. Barkatullah

IPC: G06F12/00 ,  G06F12/0893 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/0862 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32 ,  G11C11/16 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0846 ,  G06F12/0855

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US10114700B2

公开(公告)日：2018-10-30

申请号：US15347307

申请日：2016-11-09

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G06F12/00 ,  G06F11/10 ,  G06F12/0882 ,  G11C14/00

Abstract: In some examples, a memory is configured to write multiple pages of an internal page size from a cache on the memory to a memory array on the memory in response to receiving a single precharge command when in a page emulation mode. When in the page emulation mode, the memory also reads multiple pages of the internal page size from the memory array and stores them in the cache in response to receiving a single activate command.

公开(公告)号：US09990300B2

公开(公告)日：2018-06-05

申请号：US15141379

申请日：2016-04-28

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian ,  Javed S. Barkatullah

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/0862 ,  G06F3/06 ,  G06F12/0802

CPC classification number: G06F12/0893 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0862 ,  G06F2212/3042 ,  G06F2212/6026 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/1693 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2207/2272

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US09972373B2

公开(公告)日：2018-05-15

申请号：US15636970

申请日：2017-06-29

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16 ,  G11C7/06 ,  G11C7/02 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C7/02 ,  G11C7/065 ,  G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0057 ,  G11C2207/002

Abstract: An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.

公开(公告)号：US09911481B1

公开(公告)日：2018-03-06

申请号：US15445898

申请日：2017-02-28

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

CPC classification number: G11C11/1655 ,  G11C11/1657 ,  H01L27/228 ,  H01L43/08

Abstract: A selection circuit and related access circuitry that can be used for column selection in spin-torque magnetic memory is disclosed. The selection circuit can be implemented with three transistors, all of which can be NMOS transistors, thereby reducing area requirements. The selection circuit includes drive transistor that can be autobooted based on the drive voltage applied across the drive transistor. A single control signal controls the state of the selection circuit, and the selection circuits can be nested to provide multiple levels of decoding or selection.

公开(公告)号：US20170315920A1

公开(公告)日：2017-11-02

申请号：US15141379

申请日：2016-04-28

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian ,  Javed S. Barkatullah

IPC: G06F12/0893 ,  G06F3/06 ,  G06F12/0862

CPC classification number: G06F12/0893 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0862 ,  G06F2212/3042 ,  G06F2212/6026 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/1693 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2207/2272

Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.