公开(公告)号：US20060035442A1

公开(公告)日：2006-02-16

申请号：US11175912

申请日：2005-07-05

申请人： Gurkan Ilicali ,  Erhard Landgraf ,  Wolfgang Roesner ,  Franz Hofmann

发明人： Gurkan Ilicali ,  Erhard Landgraf ,  Wolfgang Roesner ,  Franz Hofmann

IPC分类号： H01L21/30

CPC分类号： H01L29/66772 ,  H01L29/66628 ,  H01L29/78648 ,  H01L29/78654

摘要： In a process for producing a layer arrangement, a first layer is formed with a thickness on a first side of a substrate, which thickness is greater than a minimum thickness for epitaxial growth, a second layer is epitaxially grown on the first layer, and a third layer is formed on the second layer. Furthermore, a handling wafer is bonded to the third layer, the substrate is removed from a second side, which is the opposite side to the first side of the substrate, and the first layer is thinned in subregions from the second side, so that after the thinning the thickness of the first layer is lower than a minimum thickness for epitaxial growth.

摘要翻译： 在制造层布置的方法中，第一层在衬底的第一侧上形成厚度，该厚度大于用于外延生长的最小厚度，第二层在第一层上外延生长，并且 第三层形成在第二层上。 此外，将处理晶片接合到第三层，从与衬底的第一侧相反的一侧的第二侧除去衬底，并且第二层在第二侧的次级区域中变薄，使得在 使第一层的厚度变薄比外延生长的最小厚度低。

公开(公告)号：US06982202B2

公开(公告)日：2006-01-03

申请号：US10899436

申请日：2004-07-26

申请人： Franz Hofmann ,  Erhard Landgraf ,  Hannes Luyken

发明人： Franz Hofmann ,  Erhard Landgraf ,  Hannes Luyken

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.

摘要翻译： 制造存储单元的方法，其中设计用于通过电荷载流子捕获进行编程的存储层和与半导体材料电绝缘的栅电极制造在半导体本体或半导体的顶侧 在设置在掺杂源极 - 漏极区之间的沟道区域之上的层结构。 该方法包括以下步骤：在顶侧制造至少一个沟槽，提供沟槽壁的至少部分，其邻接待制造的源极 - 漏极区域与存储层，将为栅电极提供的材料沉积到沟槽 通过覆盖栅极电极形成源极 - 漏极区域，在沟槽的两侧将半导体材料去除到预期深度，并且注入掺杂剂，并且向源极 - 漏极区域施加绝缘层，并且制造 栅电极的电连接。

公开(公告)号：US20050269617A1

公开(公告)日：2005-12-08

申请号：US10523944

申请日：2003-09-13

申请人： Franz Hofmann ,  Volker Lehmann ,  Lothar Risoh ,  Wolfgang Rosner ,  Michael Specht

发明人： Franz Hofmann ,  Volker Lehmann ,  Lothar Risoh ,  Wolfgang Rosner ,  Michael Specht

IPC分类号： H01L21/02 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L27/1087 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/1203 ,  H01L28/82 ,  H01L29/66181 ,  H01L29/945

摘要： A semiconductor substrate and a semiconductor circuit formed therein and associated fabrication methods are provided. A multiplicity of depressions with a respective dielectric layer and a capacitor electrode are formed for realizing buried capacitors in a carrier substrate and an actual semiconductor component layer being insulated from the carrier substrate by an insulation layer.

摘要翻译： 提供了一种形成在其中的半导体衬底和半导体电路及其制造方法。 形成具有相应电介质层和电容器电极的多个凹陷，用于在载体衬底中实现埋入式电容器，并且通过绝缘层与实施方式的半导体组件层与载体衬底绝缘。

公开(公告)号：US20050199913A1

公开(公告)日：2005-09-15

申请号：US11074345

申请日：2005-03-07

申请人： Franz Hofmann ,  Thomas Schulz ,  Michael Specht

发明人： Franz Hofmann ,  Thomas Schulz ,  Michael Specht

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： The invention relates to a semiconductor memory having a multiplicity of fins made of semiconductor material which are spaced apart from one another, a multiplicity of channel regions and contact regions being formed in each of the fins, a multiplicity of word lines, a multiplicity of storage layers, at least one of the storage layers being arranged between each of the channel regions and the word line, and a multiplicity of bit lines, the longitudinal axes of first bit line portions running parallel to a first bit line direction and the longitudinal axes of second bit line portions running parallel to a second bit line direction, the second bit line direction being rotated relative to the first bit line direction, each of the bit lines being electrically connected to a multiplicity of the contact regions, wherein, between two contact regions of the same fin that are connected to one of the bit lines, a contact region is not connected to the respective bit line.

摘要翻译： 本发明涉及一种半导体存储器，其具有由半导体材料制成的多个鳍片，它们彼此间隔开，多个通道区域和接触区域形成在每个鳍片中，多个字线，多个存储器 存储层中的至少一个布置在每个沟道区域和字线之间，并且多个位线，第一位线部分的纵向轴线平行于第一位线方向延伸，并且纵向轴线 第二位线部分平行于第二位线方向延伸，第二位线方向相对于第一位线方向旋转，每个位线电连接到多个接触区域，其中在两个接触区域之间 与位线之一连接的相同的鳍片，接触区域不连接到相应的位线。

公开(公告)号：US20050139893A1

公开(公告)日：2005-06-30

申请号：US10991345

申请日：2004-11-09

申请人： Franz Hofmann ,  Erhard Landgraf ,  Wolfgang Rosner ,  Michael Specht ,  Martin Staedele

发明人： Franz Hofmann ,  Erhard Landgraf ,  Wolfgang Rosner ,  Michael Specht ,  Martin Staedele

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L21/8242 ,  H01L29/76

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L21/845 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

摘要： In a semiconductor memory, a plurality of FinFET arrangements with trapping layers or floating gate electrodes as storage mediums are present on respective top sides of fins made from semiconductor material. The material of the gate electrodes is also present on two side walls of the fins, in order to form side wall transistors, and between the gate electrodes forms parts of a word line belonging to the corresponding fin.

摘要翻译： 在半导体存储器中，在由半导体材料制成的翅片的相应顶侧上存在多个具有捕获层或浮栅电极作为存储介质的FinFET布置。 栅电极的材料也存在于翅片的两个侧壁上，以便形成侧壁晶体管，并且在栅电极之间形成属于相应鳍片的字线的部分。

公开(公告)号：US20050048720A1

公开(公告)日：2005-03-03

申请号：US10926838

申请日：2004-08-25

申请人： Andrew Graham ,  Franz Hofmann ,  Michael Specht

发明人： Andrew Graham ,  Franz Hofmann ,  Michael Specht

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11519 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11551 ,  H01L29/66825

摘要： Floating gate memory cell having a first layer with first and second source/drain regions and a channel region arranged between and next to the first and second source/drain regions, and a floating gate layer arranged on the first layer, wherein the first and second source/drain regions and the floating gate layer are formed of a metallically conductive material, and the channel region is formed of an electrically insulating material.

摘要翻译： 具有具有第一和第二源极/漏极区域的第一层和布置在第一和第二源极/漏极区域之间和之后的沟道区域的浮动栅极存储单元以及布置在第一层上的浮动栅极层，其中第一和第二 源极/漏极区域和浮置栅极层由金属导电材料形成，并且沟道区域由电绝缘材料形成。

公开(公告)号：US06730930B2

公开(公告)日：2004-05-04

申请号：US10275598

申请日：2003-04-21

申请人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Rösner

发明人： Franz Hofmann ,  Richard Johannes Luyken ,  Wolfgang Rösner

IPC分类号： H01L3524

CPC分类号： H01L27/28 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/77 ,  H01L51/0575

摘要： A memory element with organic material comprises two metallized layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.

摘要翻译： 具有有机材料的存储元件包括两个金属化层，其一个在另一个的顶部上，第一线和第二线被布置为彼此相交。 在第一线和第二线之间的交叉处形成通道，其与第一线重叠，并且与第二线完全重叠。 通道填充有填充材料，其电导率可以通过施加的电压而改变。

公开(公告)号：US06707098B2

公开(公告)日：2004-03-16

申请号：US09882882

申请日：2001-06-15

申请人： Franz Hofmann ,  Franz Kreupl ,  Richard Johannes Luyken ,  Till Schloesser

发明人： Franz Hofmann ,  Franz Kreupl ,  Richard Johannes Luyken ,  Till Schloesser

IPC分类号： H01L29792

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C11/5671 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/81 ,  G11C2216/08 ,  H01L51/0048 ,  Y10S438/962 ,  Y10S977/943

摘要： An electronic device has a plurality of electrically conductive first nanowires, a layer system applied on the first nanowires, and also second nanowires applied on the layer system. The first and second nanowires are arranged skew with respect to one another. The layer system is set up in such a way that charge carriers generated by the nanowires can be stored in the layer system.

摘要翻译： 电子器件具有多个导电的第一纳米线，施加在第一纳米线上的层系统，以及施加在层系统上的第二纳米线。 第一和第二纳米线相对于彼此倾斜布置。 层系统的设置使得由纳米线产生的电荷载流子可以存储在层系统中。

公开(公告)号：US06599797B1

公开(公告)日：2003-07-29

申请号：US09980811

申请日：2002-03-11

申请人： Franz Hofmann ,  Josef Willer

发明人： Franz Hofmann ,  Josef Willer

IPC分类号： H01L218242

CPC分类号： H01L27/10873 ,  H01L27/10888 ,  H01L27/1203

摘要： The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO2 layer (O). An upper part of said recess (V) which is located in the range of the silicon layer (S) has cylindrical shape with a horizontal first cross-section. A lower part of the recess (V) which is located in the range of the SiO2 layer (O), compared with the upper part of the recess (V), is bulged to such an extent that it has a cylindrical shape with a horizontal second cross-section that is larger than the first cross-section. A cylinder (Z) of an insulating material is provided in the recess (V). The horizontal cross-section of said cylinder corresponds to the first cross-section and the lower part thereof is located in the lower part of the recess (V). The dent laterally surrounds the lower part of the cylinder (Z). A conducting structure (L) is located in the dent and adjoins the silicon layer (S) and the silicon substrate (1) so that the channel zone of the MOS transistors is electrically connected to the silicon substrate.

摘要翻译： 本发明涉及一种SOI衬底，其具有穿过硅层和SiO 2层（O）的凹部。 位于硅层（S）的范围内的所述凹部（V）的上部具有水平的第一横截面的圆筒形状。 与凹部（V）的上部相比，位于SiO 2层（O）的范围内的凹部（V）的下部被凸出到具有水平的圆筒形状的程度 第二横截面大于第一横截面。 在凹部（V）中设置绝缘材料的圆筒（Z）。 所述气缸的水平截面对应于第一横截面，其下部位于凹部（V）的下部。 凹陷横向围绕气缸（Z）的下部。 导电结构（L）位于凹陷中并与硅层（S）和硅衬底（1）相邻，使得MOS晶体管的沟道区电连接到硅衬底。

公开(公告)号：US06593614B1

公开(公告)日：2003-07-15

申请号：US09716336

申请日：2000-11-20

申请人： Franz Hofmann ,  Wolfgang Krautschneider

发明人： Franz Hofmann ,  Wolfgang Krautschneider

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10876

摘要： A patterned conductive layer and a structure via which a transistor can be driven, e.g. a word line, are disposed one above the other. A vertical conductive structure, e.g. a spacer, connects a first source/drain region of the transistor to the conductive layer, with which it forms a first capacitor electrode which has a large effective area in conjunction with a high packing density. A capacitor dielectric is disposed over the vertical conductive structure and the conductive layer, and a second capacitor electrode is disposed over the capacitor dielectric. The vertical conductive structure may be disposed on a first sidewall of the first source/drain region and a gate electrode of the transistor may be disposed on an adjoining second sidewall of the first source/drain region. The circuit configuration may form a DRAM cell configuration.

摘要翻译： 图案化的导电层和可以驱动晶体管的结构，例如， 一个字线，一个在另一个之上。 垂直导电结构，例如 间隔件将晶体管的第一源极/漏极区域连接到导电层，由此形成第一电容器电极，其具有大的有效面积并结合高的堆积密度。 电容器电介质设置在垂直导电结构和导电层之上，并且第二电容器电极设置在电容器电介质上。 垂直导电结构可以设置在第一源极/漏极区域的第一侧壁上，并且晶体管的栅电极可以设置在第一源极/漏极区域的相邻的第二侧壁上。 电路配置可以形成DRAM单元配置。