公开(公告)号：US20160118468A1

公开(公告)日：2016-04-28

申请号：US14523640

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. PATIL ,  Min-hwa CHI

IPC: H01L29/45 ,  H01L21/321 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/45 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/665

Abstract: There is set forth herein a method of fabricating a contact interface formation. A layer of Ti metal can be deposited on a substrate and a layer of Ni metal can be deposited over the layer of Ti metal. An annealing process can be performed to form a contact interface formation having Ti in reacted form and Ni in reacted form.

Abstract translation: 这里提出了制造接触界面形成的方法。 可以在衬底上沉积Ti金属层，并且可以在Ti金属层上沉积Ni金属层。 可以进行退火处理以形成具有反应形式的Ti和反应形式的Ni的接触界面形成。

公开(公告)号：US20160064371A1

公开(公告)日：2016-03-03

申请号：US14471712

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jian-Hsing LEE ,  Jagar SINGH ,  Manjunatha PRABHU ,  Anil KUMAR ,  Mahadeva Iyer NATARAJAN ,  Min-hwa CHI

IPC: H01L27/02 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L27/0259

Abstract: Protecting non-planar output transistors from electrostatic discharge (ESD) events includes providing a non-planar semiconductor structure, the structure including a semiconductor substrate with a well of n-type or p-type. The provided non-planar structure further includes raised semiconductor structure(s) coupled to the substrate, non-planar transistor(s) of a type opposite the well, each transistor being situated on one of the raised structure(s), the non-planar transistor(s) each including a source, a drain and a gate, the non-planar structure further including parasitic bipolar junction transistor(s) (BJT(s)) on the raised structure(s), each BJT including a collector and an emitter situated on the raised structure and a base being the well, and a well contact for the base of the BJT. Protecting the non-planar output transistors further includes electrically coupling the drain of the non-planar transistor and the collector of the BJT to an output of a circuit, and electrically coupling the source of the non-planar transistor, the emitter of the BJT and the well contact to a ground of the circuit.

Abstract translation: 保护非平面输出晶体管免受静电放电（ESD）事件包括提供非平面半导体结构，该结构包括具有n型或p型阱的半导体衬底。 提供的非平面结构还包括耦合到衬底的凸起的半导体结构，与阱相对的类型的非平面晶体管，每个晶体管位于凸起结构中的一个上， 每个包括源极，漏极和栅极的平面晶体管，非平面结构还包括在凸起结构上的寄生双极结晶体管（BJT（s）），每个BJT包括集电极和 位于凸起结构上的发射器和作为阱的基座，以及用于BJT的基座的阱接触。 保护非平面输出晶体管还包括将非平面晶体管的漏极和BJT的集电极电耦合到电路的输出，并且将非平面晶体管的源极，BJT的发射极和 接触到电路的地面。

公开(公告)号：US20150332963A1

公开(公告)日：2015-11-19

申请号：US14281454

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Changyong XIAO ,  Min-hwa CHI

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/485 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor, planar or non-planar (e.g., FinFET), includes T-shaped contacts to the source, drain and gate. The top portion of the T-shaped contact is wider than the bottom portion, the bottom portion complying with design rule limits. A conductor-material filled trench through a multi-layer etching stack above the transistor provides the top portions of the T-shaped contacts. Tapered spacers along inner sidewalls of the top contact portion prior to filling allow for etching a narrower bottom trench down to the gate, and to the source/drain for silicidation prior to filling.

Abstract translation: 晶体管，平面或非平面（例如，FinFET）包括到源极，漏极和栅极的T形接触。 T形接触件的顶部比底部宽，底部符合设计规则限制。 通过晶体管上方的多层蚀刻堆叠的导体材料填充沟槽提供了T形触头的顶部。 在填充之前，顶部接触部分的内侧壁上的锥形间隔物允许在填充之前将较窄的底部沟槽蚀刻到栅极和源极/漏极以进行硅化。

公开(公告)号：US20150228648A1

公开(公告)日：2015-08-13

申请号：US14175827

申请日：2014-02-07

Applicant: Globalfoundries Inc.

Inventor： Min-hwa CHI ,  Ajey JACOB ,  Abhijeet PAUL

IPC: H01L27/088 ,  H01L29/161 ,  H01L21/308 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract translation: 公开了一种形成具有小占地面积的多值逻辑晶体管的方法和所得到的器件。 实施例包括在硅衬底上形成多个翅片，每个翅片用硬掩模覆盖; 用氧化物填充翅片和硬掩模之间的空间; 去除硬掩模并使每个翅片凹陷，在每个翅片上的氧化物中形成空腔; 在每个空腔中形成多个Si基层，其中Ge或C的百分比增加或掺杂剂浓度从底层到顶层的浓度降低; 执行CMP以平坦化到翅片的顶部; 将氧化物凹陷到具有等于每个Si基层的厚度的厚度的略微低于翅片顶部的深度; 以及在多个Si基层上形成高k栅极电介质和金属栅电极。

公开(公告)号：US20150200251A1

公开(公告)日：2015-07-16

申请号：US14156018

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI ,  Yanxiang LIU

IPC: H01L29/06 ,  H01L29/78 ,  G11C17/16 ,  H01L29/66

CPC classification number: H01L29/0649 ,  G11C17/16 ,  H01L21/2822 ,  H01L23/5252 ,  H01L27/11206 ,  H01L29/0615 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process and device are provided for a high-k gate-dielectric operating as a built-in e-fuse. Embodiments include: providing first and second active regions of a transistor, separated by a gate region of the transistor, on a substrate; forming an interfacial layer on the gate region; minimizing the interfacial layer; forming a high-k gate dielectric layer on the interfacial layer to operate as an e-fuse element, the high-k gate dielectric layer and interfacial layer having a combined breakdown voltage less than three times a circuit operating voltage associated with the transistor; and forming a metal gate on the high-k gate dielectric layer.

Abstract translation: 为作为内置电子熔断器操作的高k栅介质提供了一种工艺和器件。 实施例包括：在衬底上提供由晶体管的栅极区分隔开的晶体管的第一和第二有源区; 在栅极区上形成界面层; 最小化界面层; 在所述界面层上形成高k栅介质层，以作为e熔丝元件工作，所述高k栅介质层和界面层的组合击穿电压小于与所述晶体管相关联的电路工作电压的三倍; 并在高k栅极电介质层上形成金属栅极。

公开(公告)号：US20150137235A1

公开(公告)日：2015-05-21

申请号：US14083164

申请日：2013-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin.

Abstract translation: 这里在一个实施例中阐述了具有从体硅衬底延伸的翅片的FinFET半导体器件，其中形成为围绕鳍的一部分围绕栅极缠绕，并且其中靠近与栅极对准的鳍的沟道区域 形成与栅极对准的局部掩埋氧化物区域。 在一个实施例中，局部掩埋氧化物区域形成在鳍片的沟道区域的下方。