公开(公告)号：US5940319A

公开(公告)日：1999-08-17

申请号：US144686

申请日：1998-08-31

申请人： Mark Durlam ,  Gloria Kerszykowski ,  Jon Slaughter ,  Theodore Zhu ,  Eugene Chen ,  Saied N. Tehrani ,  Kelly W. Kyler

发明人： Mark Durlam ,  Gloria Kerszykowski ,  Jon Slaughter ,  Theodore Zhu ,  Eugene Chen ,  Saied N. Tehrani ,  Kelly W. Kyler

IPC分类号： G11C11/15 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/14

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/224

摘要： An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).

摘要翻译： 提供了一种具有磁存储器元件和用于控制磁存储元件的电路的改进和新颖的MRAM器件。 电路，例如具有栅极（17a），漏极（18）和源极（16a）的晶体管（12a）集成在衬底（11）上并且耦合到电路上的磁存储元件（43），通过 插头导体（19a）和导线（45）。 首先在CMOS工艺之下制造电路，然后制造磁存储元件（43,44）。 数字线（29）和位线（48）分别放置在磁存储元件（43）的下面和顶部，并且能够访问磁存储元件（43）。 这些线被除了面向磁性存储元件（43）的高磁导率层（31,56,58）包围，磁性层屏蔽并将磁场聚焦到磁性存储元件（43）。

公开(公告)号：US5838608A

公开(公告)日：1998-11-17

申请号：US874436

申请日：1997-06-16

申请人： Theodore Zhu ,  Saied N. Tehrani

发明人： Theodore Zhu ,  Saied N. Tehrani

IPC分类号： G11C11/15

CPC分类号： G11C11/15

摘要： A new magnetic random access memory (MRAM) unit (30) is provided suitable for fabricating a MRAM device (20). The MRAM cell includes a magnetic storage element (32) and a current control element (33), for example, a diode, connected to the magnetic storage element in series to control a current in the magnetic storage element. The magnetic storage element has two magnetoresistive layers (36,38) separated by a non-magnetic layer (37), for example, aluminum oxide (Al.sub.2 O.sub.3). The diode allows a current to flow in only an MRAM cell activated by a column line and a row line.

摘要翻译： 提供了适合于制造MRAM装置（20）的新的磁性随机存取存储器（MRAM）单元（30）。 MRAM单元包括串联连接到磁存储元件的磁存储元件（32）和电流控制元件（33），例如二极管，以控制磁存储元件中的电流。 磁存储元件具有由非磁性层（37）分隔的两个磁阻层（36,38），例如氧化铝（Al 2 O 3）。 二极管允许电流仅流过由列线和行线激活的MRAM单元。

公开(公告)号：US5733827A

公开(公告)日：1998-03-31

申请号：US557405

申请日：1995-11-13

申请人： Saied N. Tehrani ,  Mark Durlam ,  Marino J. Martinez ,  Jenn-Hwa Huang ,  Ernie Schirmann

发明人： Saied N. Tehrani ,  Mark Durlam ,  Marino J. Martinez ,  Jenn-Hwa Huang ,  Ernie Schirmann

IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L23/485 ,  H01L21/28 ,  H01L21/337

CPC分类号： H01L29/66863 ,  H01L21/28587 ,  H01L23/485 ,  H01L2924/0002

摘要： A method of fabricating semiconductor devices with a passivated surface includes providing first cap and etch stop layers and second cap and etch stop layers with a contact layer thereon so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually etched to define an electrode contact area and to expose the inter-electrode surface area. Portions of the first etch stop and cap layers remaining in the contact area are selectively removed and a metal contact is formed in the contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

摘要翻译： 制造具有钝化表面的半导体器件的方法包括提供第一帽和蚀刻停止层以及其上具有接触层的第二帽和蚀刻停止层，以限定电极间表面积。 相对于彼此可选择性地蚀刻的第一层和绝缘层沉积在接触层和电极间表面区域上。 绝缘层和第一层被单独蚀刻以限定电极接触面积并暴露电极间表面积。 选择性地除去残留在接触区域中的第一蚀刻停止层和盖层的部分，并且在与绝缘层邻接接合的接触区域中形成金属接触，以密封电极间表面积。

公开(公告)号：US5550065A

公开(公告)日：1996-08-27

申请号：US344911

申请日：1994-11-25

申请人： Majid M. Hashemi ,  Saied N. Tehrani ,  Patricia A. Norton

发明人： Majid M. Hashemi ,  Saied N. Tehrani ,  Patricia A. Norton

IPC分类号： H01L21/285 ,  H01L21/338 ,  H01L29/417 ,  H01L29/423 ,  H01L29/47 ,  H01L21/265

CPC分类号： H01L29/66878 ,  H01L21/28587 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/475 ,  Y10S148/003 ,  Y10S148/10 ,  Y10S148/131 ,  Y10S148/14

摘要： A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.

摘要翻译： 制造具有GaAs或InP的半绝缘衬底的自对准FET的方法，其具有通过在邻近表面的衬底中通过分子束外延或金属有机气相外延掺杂表面或外延生长的沟道而形成的导电沟道。 在衬底表面形成高温稳定的LaB6 / TiWN“T型”肖特基栅极接触，用于源极和漏极欧姆区注入到与衬底相邻的衬底中并与“T形”栅极自对准 源极和漏极欧姆触点也相对于栅极自对准。

公开(公告)号：US5514606A

公开(公告)日：1996-05-07

申请号：US270275

申请日：1994-07-05

申请人： Majid M. Hashemi ,  Saied N. Tehrani

发明人： Majid M. Hashemi ,  Saied N. Tehrani

IPC分类号： H01L21/338 ,  H01L23/31 ,  H01L29/812

CPC分类号： H01L29/66863 ,  H01L23/3171 ,  H01L29/812 ,  H01L29/8128 ,  H01L2924/0002 ,  H01L2924/13063

摘要： A method of fabricating high breakdown voltage MESFETs forming a conduction channel in a GaAs substrate adjacent the surface, forming high temperature stable source and drain ohmic contacts and a Schottky gate contact on the surface of the substrate in overlying relationship to the channel and in spaced relationship, and depositing a layer of low temperature GaAs passivation material over the substrate surface and the source, drain and gate contacts. Openings are then etched in the passivation material for contacting the source, drain and gate contacts.

摘要翻译： 制造在击穿表面附近的GaAs衬底中形成导电沟道的高耐压MESFET的方法，在衬底的表面上形成高温稳定的源极和漏极欧姆接触和肖特基门接触，并以间隔的关系 ，并在衬底表面和源极，漏极和栅极触点上沉积一层低温GaAs钝化材料。 然后在钝化材料中蚀刻开口以接触源极，漏极和栅极触点。

公开(公告)号：US5400352A

公开(公告)日：1995-03-21

申请号：US210851

申请日：1994-03-21

申请人： Michael S. Lebby ,  Saied N. Tehrani

发明人： Michael S. Lebby ,  Saied N. Tehrani

IPC分类号： H01L33/00 ,  H01S5/00 ,  H01S5/34 ,  H01S5/343 ,  H01S3/19

CPC分类号： B82Y20/00 ,  H01S5/34 ,  H01S5/343 ,  H01S5/34313 ,  H01S5/0021 ,  H01S5/3432 ,  Y10S438/936

摘要： A semiconductor laser (10) utilizes a material having a first band gap (26) for an active layer (13) of the laser (10). Monolayers (14) of a material having a smaller band gap are positioned in the active layer (13) without substantially altering the first band gap (26). The monolayers (14) have a combined thickness that is more than approximately 15 percent of the thickness (16) of the active layer (13).

摘要翻译： 半导体激光器（10）利用具有用于激光器（10）的有源层（13）的第一带隙（26）的材料。 具有较小带隙的材料的单层（14）位于有源层（13）中，而基本上不改变第一带隙（26）。 单层（14）具有大于活性层（13）的厚度（16）的约15％的组合厚度。

公开(公告)号：US06174737B1

公开(公告)日：2001-01-16

申请号：US09339460

申请日：1999-06-24

申请人： Mark Durlam ,  Gloria Kerszykowski ,  Jon Slaughter ,  Theodore Zhu ,  Eugene Chen ,  Saied N. Tehrani ,  Kelly W. Kyler

发明人： Mark Durlam ,  Gloria Kerszykowski ,  Jon Slaughter ,  Theodore Zhu ,  Eugene Chen ,  Saied N. Tehrani ,  Kelly W. Kyler

IPC分类号： H01L2100

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/224

摘要： An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).

摘要翻译： 提供了一种具有磁存储器元件和用于控制磁存储元件的电路的改进和新颖的MRAM器件。 电路，例如具有栅极（17a），漏极（18）和源极（16a）的晶体管（12a）集成在衬底（11）上并且耦合到电路上的磁存储元件（43），通过 插头导体（19a）和导线（45）。 首先在CMOS工艺之下制造电路，然后制造磁存储元件（43,44）。 数字线（29）和位线（48）分别放置在磁存储元件（43）的下面和顶部，并且能够访问磁存储元件（43）。 这些线被除了面向磁性存储元件（43）的高磁导率层（31,56,58）包围，磁性层屏蔽并将磁场聚焦到磁性存储元件（43）。

公开(公告)号：US5828598A

公开(公告)日：1998-10-27

申请号：US862738

申请日：1997-05-23

申请人： Eugene Chen ,  Saied N. Tehrani ,  David W. Cronk

发明人： Eugene Chen ,  Saied N. Tehrani ,  David W. Cronk

IPC分类号： G11C11/15 ,  G11C7/00

CPC分类号： G11C11/15

摘要： A magnetic memory cell with increased GMR ratio includes first and second layers of magnetic material stacked in parallel, overlying relationship and separated by a layer of non-magnetic material sandwiched between the first and second layers of magnetic material. Each of the first and second layers is switchable between a first and a second magnetic state and is formed to switch states with the application of a substantially equal magnetic field. A third layer of magnetic material is positioned adjacent one of the first and second layers of magnetic material so as to alter the amount of magnetic field required to switch the states of the one of the first and second layers of magnetic material. The third layer of magnetic material can be formed with a width larger than the cell width to increase the magnetic width of the cell and reduce the magnetic field required to switch states.

摘要翻译： 具有增加的GMR比率的磁存储单元包括平行堆叠的第一和第二层磁性材料，覆盖关系并由夹在第一和第二磁性层之间的非磁性材料层分开。 第一层和第二层中的每一层可在第一和第二磁状态之间切换，并且形成为通过施加基本相等的磁场来切换状态。 磁性材料的第三层位于第一和第二磁性层之一附近，以改变切换第一和第二磁性层之一的状态所需的磁场的量。 可以形成具有大于单元宽度的宽度的第三层磁性材料以增加单元的磁宽度并减小开关状态所需的磁场。

公开(公告)号：US5774394A

公开(公告)日：1998-06-30

申请号：US862090

申请日：1997-05-22

申请人： Eugene Chen ,  Saied N. Tehrani ,  Steven A. Voight

发明人： Eugene Chen ,  Saied N. Tehrani ,  Steven A. Voight

IPC分类号： G11C11/16 ,  H01F10/32 ,  G11C11/15

CPC分类号： B82Y25/00 ,  G11C11/16 ,  H01F10/3268

摘要： A first layer of non-magnetic material is positioned on a layer of an oxide of a magnetic material (e.g. NiO). First and second layers of magnetic material are stacked in parallel, overlying relationship and separated by a second layer of non-magnetic material sandwiched therebetween to form a magnetic memory cell. The magnetic memory cell is positioned on the first layer of nonmagnetic material so as to sandwich the first nonmagnetic layer between the oxide and the first magnetic layer of the cell. The first layer of non-magnetic material has a thickness (e.g. approximately 7 .ANG.) which prevents the oxide from pinning the first layer of magnetic material and adapts the first layer of magnetic material to the layer of oxide so as to increase the GMR ratio of the magnetic memory cell.

摘要翻译： 第一层非磁性材料位于磁性材料（例如NiO）的氧化物层上。 第一和第二层磁性材料层叠在一起，叠置关系并被夹在其间的非磁性材料的第二层隔开以形成磁存储单元。 磁存储单元位于非磁性材料的第一层上，以将第一非磁性层夹在电池的氧化物和第一磁性层之间。 第一层非磁性材料具有厚度（例如约7安格姆），其防止氧化物钉住第一层磁性材料并使第一层磁性材料适应于氧化物层，以便增加GMR比值 磁性存储单元。

公开(公告)号：US5757695A

公开(公告)日：1998-05-26

申请号：US795488

申请日：1997-02-05

申请人： Jing Shi ,  Theodore Zhu ,  Saied N. Tehrani

发明人： Jing Shi ,  Theodore Zhu ,  Saied N. Tehrani

IPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/56 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/10

CPC分类号： G11C11/5607 ,  G11C11/15 ,  G11C11/16 ,  G11C2211/5616

摘要： A multi-layer magnetic memory cell is provided, with magnetic vectors aligned along a length of the cell. To align the magnetic end vectors, an ellipsoidal shape is formed at the ends of the memory cell. Magnetic vectors aligned along the length prevent from forming high fields and magnetic poles at the discontinuity or ends of the layers. The memory cell with the ellipsoidal shape shows a constant magnetic resistance of the magnetic cell when a magnetic field is applied to the cell and attains a reduction of power consumption for the magnetic cell.

摘要翻译： 提供了多层磁存储单元，其中磁矢量沿单元的长度排列。 为了对准磁端向量，在存储单元的端部形成椭圆形状。 沿着长度排列的磁矢量防止在层的不连续或端部处形成高场和磁极。 具有椭圆形状的存储单元在磁场施加到电池并且降低磁性单元的功耗时显示出磁性单元的恒定的磁阻。