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61.发明授权Wiring over substrate, semiconductor device, and methods for manufacturing thereof 有权衬底上的接线，半导体器件及其制造方法公开(公告)号：US08669663B2
公开(公告)日：2014-03-11
申请号：US13187746
申请日：2011-07-21
申请人： Shinya Sasagawa , Satoru Okamoto , Shigeharu Monoe
发明人： Shinya Sasagawa , Satoru Okamoto , Shigeharu Monoe
IPC分类号： H01L23/48
CPC分类号： H01L27/3276 , G02F2001/13629 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L51/0021 , H01L51/0023 , H01L51/5281 , H01L2924/0002 , H05K3/06 , H05K2203/0315 , H05K2203/0346 , H05K2203/095 , H05K2203/1476 , H01L2924/00
摘要： A wiring over a substrate capable of reducing particles between wirings and a method for manufacturing the wiring is disclosed. A wiring over a substrate capable of preventing short-circuiting between wirings due to big difference in projection and depression between wirings and a method for manufacturing the wiring is also disclosed. Further, a wiring over a substrate capable of preventing cracks in the insulating layer due to stress at the edge of a wiring or particles and a method for manufacturing the wiring is also disclosed. According to the present invention, a method for manufacturing a wiring over a substrate is provided that comprises the steps of: forming a first conductive layer over an insulating surface; forming a first mask pattern over the first conductive layer; forming a second mask pattern by etching the first mask pattern under a first condition, simultaneously, forming a second conductive layer having a side having an angle of inclination cross-sectionally by etching the first conductive layer; and forming a third conductive layer and a third mask pattern by etching the second conductive layer and the second mask pattern under a second condition; wherein a selective ratio under the first condition of the first conductive layer to the first mask pattern is in a range of 0.25 to 4, and a selective ratio under the second condition of the second conductive layer to the second mask pattern is larger than that under the first condition.
摘要翻译： 公开了一种能够减少布线之间的颗粒的基板上的布线和用于制造布线的方法。 还公开了一种能够防止布线之间的大的差异和配线间的凹陷之间的布线之间的短路的布线和布线的制造方法。 此外，还公开了能够防止由于布线或颗粒的边缘处的应力导致的绝缘层中的裂纹的基板上的布线以及布线的制造方法。 根据本发明，提供了一种用于在衬底上制造布线的方法，包括以下步骤：在绝缘表面上形成第一导电层; 在所述第一导电层上形成第一掩模图案; 通过在第一条件下蚀刻第一掩模图案形成第二掩模图案，同时通过蚀刻第一导电层形成具有横截面为倾斜角的一侧的第二导电层; 以及通过在第二条件下蚀刻所述第二导电层和所述第二掩模图案来形成第三导电层和第三掩模图案; 其中在第一导电层与第一掩模图案的第一条件下的选择比在0.25至4的范围内，并且在第二导电层与第二掩模图案的第二条件下的选择比大于 第一个条件。
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公开(公告)号：US08476122B2
公开(公告)日：2013-07-02
申请号：US13273267
申请日：2011-10-14
申请人： Shinya Sasagawa , Hiroshi Fujiki
发明人： Shinya Sasagawa , Hiroshi Fujiki
IPC分类号： H01L21/00
CPC分类号： H01L21/32137 , H01L29/04 , H01L29/66765 , H01L29/78696
摘要： A method for manufacturing a semiconductor device with high electric characteristics is provided. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas including an HBr gas, a CF4 gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Etching for forming a back channel portion of a thin film transistor is performed with the method for etching, whereby high electric characteristics can be provided for the thin film transistor.
摘要翻译： 提供一种制造具有高电特性的半导体器件的方法。 使用包含HBr气体，CF4气体和氧气的混合气体蚀刻在结晶半导体膜上设置非晶半导体膜的层叠半导体膜的一部分，使得设置在晶体半导体膜中的部分结晶半导体膜 堆叠的半导体膜被暴露。 通过蚀刻方法进行用于形成薄膜晶体管的背沟道部分的蚀刻，由此可以为薄膜晶体管提供高电特性。
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公开(公告)号：US20130071762A1
公开(公告)日：2013-03-21
申请号：US13610951
申请日：2012-09-12
申请人： Ryota TAJIMA , Shunpei Yamazaki , Teppei Oguni , Takeshi Osada , Shinya Sasagawa , Kazutaka Kuriki
发明人： Ryota TAJIMA , Shunpei Yamazaki , Teppei Oguni , Takeshi Osada , Shinya Sasagawa , Kazutaka Kuriki
CPC分类号： H01M4/133 , B82Y30/00 , H01M4/134 , H01M4/1395 , H01M4/366 , H01M4/386 , H01M4/625 , H01M10/0525 , H01M10/465 , Y02E60/122 , Y02T10/7011
摘要： A power storage device which has high charge/discharge capacity and less deterioration in battery characteristics due to charge/discharge and can perform charge/discharge at high speed is provided. A power storage device includes a negative electrode. The negative electrode includes a current collector and an active material layer provided over the current collector. The active material layer includes a plurality of protrusions protruding from the current collector and a graphene provided over the plurality of protrusions. Axes of the plurality of protrusions are oriented in the same direction. A common portion may be provided between the current collector and the plurality of protrusions.
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公开(公告)号：US08242494B2
公开(公告)日：2012-08-14
申请号：US12582082
申请日：2009-10-20
申请人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka , Shunichi Ito , Miyuki Hosoba
发明人： Hideomi Suzawa , Shinya Sasagawa , Taiga Muraoka , Shunichi Ito , Miyuki Hosoba
IPC分类号： H01L29/786
CPC分类号： H01L29/66969 , H01L27/1225 , H01L27/1288 , H01L29/66742 , H01L29/78621 , H01L29/7869
摘要： An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.
摘要翻译： 目的是以低成本，高生产率制造包括氧化物半导体的半导体器件，使得通过减少曝光掩模的数量来简化光刻工艺。 在制造包括通道蚀刻反交错薄膜晶体管的半导体器件的方法中，使用使用作为曝光的多色调掩模形成的掩模层来蚀刻氧化物半导体膜和导电膜 光透过该掩模以具有多个强度。 在蚀刻步骤中，通过使用蚀刻剂的湿式蚀刻进行第一蚀刻步骤，并且通过使用蚀刻气体的干法蚀刻进行第二蚀刻步骤。
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公开(公告)号：US08227278B2
公开(公告)日：2012-07-24
申请号：US12545276
申请日：2009-08-21
IPC分类号： H01L33/00 , H01L21/336
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1255 , H01L29/04 , H01L29/41733 , H01L29/66765 , H01L29/78696
摘要： The present invention provides a method for manufacturing a thin film transistor with small leakage current and high switching characteristics. In a method for manufacturing a thin film transistor, a back channel portion is formed in the thin film transistor by conducting etching using a resist mask, the resist mask is removed by removal or the like, and a superficial part of the back channel portion is further etched. Through the steps, components of chemical solution used for the removal, residues of the resist mask, and the like which exist at the superficial part of the back channel portion can be removed and leakage current can be reduced. The further etching step of the back channel portion is preferably conducted by dry etching using an N2 gas or a CF4 gas with bias not applied.
摘要翻译： 本发明提供一种制造漏电流小，开关特性高的薄膜晶体管的制造方法。 在制造薄膜晶体管的方法中，通过使用抗蚀剂掩模进行蚀刻，在薄膜晶体管中形成背沟道部分，通过去除等除去抗蚀剂掩模，并且背沟道部分的表面部分是 进一步刻蚀。 通过这些步骤，可以去除存在于背部通道部分的表面部分的用于去除的化学溶液的组分，抗蚀剂掩模的残留物等，并且可以减少泄漏电流。 后通道部分的进一步蚀刻步骤优选通过使用N 2气体或没有施加偏压的CF 4气体进行干蚀刻来进行。
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公开(公告)号：US08067772B2
公开(公告)日：2011-11-29
申请号：US11949186
申请日：2007-12-03
IPC分类号： H01L29/04
CPC分类号： H01L27/12 , H01L29/66757 , H01L29/78675 , Y10T428/24421
摘要： An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.
摘要翻译： 本发明的目的是提供一种可靠性提高的半导体器件及其制造方法，该半导体器件具有提高的岛状半导体层的端部的缺陷。 一种结构包括设置在基板上的岛状半导体层，设置在岛状半导体层的顶表面和侧表面上的绝缘层以及设置在岛状半导体层上的绝缘层的栅电极 插入其间。 在与岛状半导体层接触的绝缘层中，使与岛状半导体层的侧面接触的区域的介电常数比上述表面的区域低 岛状半导体层。
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公开(公告)号：US20110147744A1
公开(公告)日：2011-06-23
申请号：US12972859
申请日：2010-12-20
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L29/66765 , H01L29/786 , H01L29/78663
摘要： An object is to increase the on-state current of a thin film transistor. A solution is to provide a projection in a back-channel portion of the thin film transistor. The projection is provided so as to be off a tangent in the back-channel portion between a source or a drain and a channel formation region. With the projection, a portion where electric charge is trapped and a path of the on-state current can be apart from each other, so that the on-state current can be increased. The shape of a side surface of the back-channel portion may be curved, or may be represented as straight lines in a cross section. Further, a method for forming such a shape by performing one etching step is provided.
摘要翻译： 目的是增加薄膜晶体管的导通电流。 解决方案是在薄膜晶体管的后通道部分中提供投影。 突起被设置成在源极或漏极之间的后部沟道部分和沟道形成区域之间切断切线。 通过投影，电荷被捕获的部分和导通状态电流的路径可以彼此分开，从而可以增加导通电流。 背沟道部分的侧表面的形状可以是弯曲的，或者可以在横截面中表示为直线。 此外，提供了通过执行一个蚀刻步骤来形成这种形状的方法。
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68.发明授权公开(公告)号：US07791154B2
公开(公告)日：2010-09-07
申请号：US12575910
申请日：2009-10-08
IPC分类号： H10L31/075 , H01L31/18
CPC分类号： H01L31/035281 , H01L21/32136 , H01L21/32137 , H01L27/14643 , Y02E10/50
摘要： An object is to provide a photoelectric conversion element having a side surface with different taper angles by conducting etching of a photoelectric conversion layer step-by-step. A pin photodiode has a high response speed compared with a pn photodiode but has a disadvantage of large dark current. One cause of the dark current is considered to be conduction through an etching residue which is generated in etching and deposited on a side surface of the photoelectric conversion layer. Leakage current of the photoelectric conversion element is reduced by forming a structure in which a side surface has two different tapered shapes, which conventionally has a uniform surface, so that the photoelectric conversion layer has a side surface of a p-layer and a side surface of an n-layer, which are not in the same plane.
摘要翻译： 本发明的目的是提供一种具有不同锥角的侧面的光电转换元件，该光电转换元件逐步进行光电转换层的蚀刻。 与pn光电二极管相比，pin光电二极管具有高响应速度，但是具有大的暗电流的缺点。 认为暗电流的一个原因是通过在蚀刻中产生并沉积在光电转换层的侧表面上的蚀刻残余物导电。 光电转换元件的泄漏电流通过形成侧表面具有两个不同的锥形形状的结构而降低，通常具有均匀的表面，使得光电转换层具有p层的侧表面和侧表面 的n层，它们不在同一平面。
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公开(公告)号：US20080128808A1
公开(公告)日：2008-06-05
申请号：US11945739
申请日：2007-11-27
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/4908 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78609
摘要： A semiconductor device manufactured utilizing an SOI substrate, in which defects due to an end portion of an island-shaped silicon layer are prevented and the reliability is improved, and a manufacturing method thereof. The following are included: an SOI substrate in which an insulating layer and an island-shaped silicon layer are stacked in order over a support substrate; a gate insulating layer provided over one surface and a side surface of the island-shaped silicon layer; and a gate electrode which is provided over the island-shaped silicon layer with the gate insulating layer interposed therebetween. The gate insulating layer is formed such that the dielectric constant in the region which is in contact with the side surface of the island-shaped silicon layer is lower than that over the one surface of the island-shaped silicon layer.
摘要翻译： 利用SOI衬底制造的半导体器件及其制造方法，其中防止了由岛状硅层的端部引起的缺陷并提高了可靠性。 包括以下：SOI基板，其中绝缘层和岛状硅层依次层叠在支撑基板上; 设置在岛状硅层的一个表面和侧面上的栅极绝缘层; 以及栅极电极，其设置在岛状硅层上，栅极绝缘层插入其间。 栅极绝缘层形成为与岛状硅层的侧面接触的区域的介电常数低于岛状硅层的一个表面的介电常数。
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公开(公告)号：US07253044B2
公开(公告)日：2007-08-07
申请号：US11524958
申请日：2006-09-22
IPC分类号： H01L21/336
CPC分类号： H01L29/66757 , H01L21/32136 , H01L21/32139 , H01L29/42384 , H01L29/78621 , H01L2029/7863
摘要： With respect to the selective ratio in the etching process, it is an object to give design freedom in size of an LDD overlapped with a gate electrode, which is formed in a self-aligning manner, by performing an etching process under an etching condition that has a high selective ratio between a mask pattern and metal such as titanium in forming a first conductive layer pattern. A laminated structure comprising a lower first conductive layer and an upper second conductive layer is formed over a semiconductor layer with a gate insulating film interposed therebetween, a mask pattern is formed on the laminated structure, a condition that an etching rate of the mask pattern is fast is used and the second conductive layer and the first conductive layer are etched to form a tapered first conductive layer pattern, and the second conductive layer in the first conductive layer pattern is selectively etched in accordance with the left mask pattern to form a second conductive layer pattern in which a width of the first conductive layer is longer than that of the second conductive layer.
摘要翻译： 关于蚀刻工艺中的选择比，目的是通过在蚀刻条件下进行蚀刻工艺，以自对准方式形成与栅电极重叠的LDD的尺寸设计自由度， 在形成第一导电层图案时，在掩模图案和诸如钛的金属之间具有高的选择比。 在半导体层上形成包括下部第一导电层和上部第二导电层的层叠结构，其间具有栅极绝缘膜，在层叠结构上形成掩模图案，掩模图案的蚀刻速率为 并且第二导电层和第一导电层被蚀刻以形成渐缩的第一导电层图案，并且根据左掩模图案选择性地蚀刻第一导电层图案中的第二导电层以形成第二导电层 所述第一导电层的宽度比所述第二导电层的宽度长。
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