公开(公告)号：US20210382805A1

公开(公告)日：2021-12-09

申请号：US16896070

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Nimrod Angel ,  Ameya Ambardekar ,  Sapumal Wijeratne ,  Vikas Vij ,  Tod Schiff ,  Alexander Uan-Zo-Li

IPC: G06F11/30 ,  G06F11/07 ,  G06F1/3296 ,  G06F9/4401 ,  G06F9/30

Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 μS) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).

公开(公告)号：US10990395B2

公开(公告)日：2021-04-27

申请号：US16666111

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Eliezer Weissmann ,  Michael Mishaeli

IPC: G06F9/30 ,  G06F9/54 ,  G06F9/50

Abstract: A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the remote circuit including a remote register. The register management array circuit includes circuitry to cause the data in the local core register to match the data in the remote register. Methods and circuits are also disclosed.

公开(公告)号：US10928886B2

公开(公告)日：2021-02-23

申请号：US16285051

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Praveen Mosalikanti ,  Nasser A. Kurd ,  Alexander Gendler

IPC: G06F1/3296 ,  H03L7/093 ,  G01R19/25 ,  H03L7/095 ,  H03K5/24 ,  H03K19/20

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

公开(公告)号：US10719326B2

公开(公告)日：2020-07-21

申请号：US15886313

申请日：2018-02-01

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Ariel Szapiro

IPC: G06F1/26 ,  G06F9/38 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/324

Abstract: In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.

公开(公告)号：US10705559B2

公开(公告)日：2020-07-07

申请号：US16189973

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Kosta Luria ,  Arye Albahari ,  Ohad Nachshon

IPC: G06F1/08 ,  G06F1/3206 ,  G06F1/3296 ,  G06F1/324 ,  G01R19/165 ,  G06F1/06 ,  G06F1/26 ,  G01R1/20 ,  G01R19/00

Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.

公开(公告)号：US20200012333A1

公开(公告)日：2020-01-09

申请号：US16572747

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Arkady Bramnik ,  Lev Makovsky

IPC: G06F1/3287 ,  G06F1/324 ,  G06F11/10

Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.

公开(公告)号：US10345889B2

公开(公告)日：2019-07-09

申请号：US15668762

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/07

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US20190171273A1

公开(公告)日：2019-06-06

申请号：US16261370

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Alexander Gendler

IPC: G06F1/324 ,  G06F1/3296 ,  G06F1/3206

Abstract: Methods and apparatus relating to techniques for processor core energy management are described. In an embodiment, energy management logic causes a modification to energy consumption by an electrical load (such as a processor core) based at least in part on comparison of an electrical current value and an operating current threshold value. The electrical current value is detected at an electrical current sensor coupled to the electrical load. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190004583A1

公开(公告)日：2019-01-03

申请号：US15638573

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Yiftach Gilad ,  Ariel Szapiro ,  Elkana Korem ,  Alexander Gendler

IPC: G06F1/32 ,  G06F1/08 ,  H03K5/133 ,  H03K19/003 ,  G11C7/22 ,  G11C5/14

Abstract: Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.

公开(公告)号：US20180120924A1

公开(公告)日：2018-05-03

申请号：US15668762

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC: G06F1/32 ,  G06F11/07

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.