公开(公告)号：US11430724B2

公开(公告)日：2022-08-30

申请号：US16646529

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Robert L. Sankman ,  Robert Nickerson ,  Mitul Modi ,  Sanka Ganesan ,  Rajasekaran Swaminathan ,  Omkar Karhade ,  Shawna M. Liff ,  Amruthavalli Alur ,  Sri Chaitra J. Chavali

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：US20220102231A1

公开(公告)日：2022-03-31

申请号：US17032583

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Mitul Modi ,  Joseph Van Nausdle ,  Omkar Karhade ,  Edvin Cetegen ,  Nicholas Haehn ,  Vaibhav Agrawal ,  Digvijay Raorane

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/16 ,  H01L25/065

Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled thereto. A dummy die structure extends to a bottom of a recess structure formed by a first package mold structure on the substrate. The dummy die structure comprises a polymer resin and a filler, or comprises a metal which has a low coefficient of thermal expansion (CTE). A second package mold structure, which extends to the recess structure, is adjacent to the first package mold structure and to an IC die. In another embodiment, a first CTE of the dummy die is less than a second CTE of one of the package mold structures, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the one of the package mold structures.

公开(公告)号：US20210366862A1

公开(公告)日：2021-11-25

申请号：US17392598

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Zhaozhi Li ,  Sanka Ganesan ,  Debendra Mallik ,  Gregory Perry ,  Kuan H. Lu ,  Omkar Karhade ,  Shawna M. Liff

IPC: H01L23/00

Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.

公开(公告)号：US20200273811A1

公开(公告)日：2020-08-27

申请号：US16287665

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Mitul Modi ,  Sanka Ganesan ,  Edvin Cetegen ,  Omkar Karhade ,  Ravindranath Mahajan ,  James C. Matayabas, Jr. ,  Jan Krajniak ,  Kumar Singh ,  Aastha Uppal

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/29 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56 ,  H01L23/532

Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.

公开(公告)号：US20200227332A1

公开(公告)日：2020-07-16

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, JR.

IPC: H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US20200066659A1

公开(公告)日：2020-02-27

申请号：US16107791

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Omkar Karhade ,  Martin Rodriguez ,  Gregorio R. Murtagian

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/495 ,  H01F27/24 ,  H01L49/02

Abstract: A microelectronics package, comprising a substrate comprising a first bondpad and a second bondpad over a dielectric. An inductor comprising at least one wire extends over the dielectric. The at least one wire has a first end coupled to the first bondpad and a second end coupled to the second bondpad, and an inductor core layer over the dielectric. The inductor core layer comprises a magnetic material. At least a portion of the inductor extends within the inductor core layer.

公开(公告)号：US20180358274A1

公开(公告)日：2018-12-13

申请号：US15778387

申请日：2016-11-11

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Kedar Dhane

IPC: H01L23/16

Abstract: An electronic package that includes a substrate; a die attached to the substrate; an underfill positioned between the die and the substrate due to capillary action; a first support adjacent to the die and attached to the substrate; and a second support mounted on the first support, wherein the second support is closer to the die than the first support, wherein first support surrounds the die and the second support surrounds the die, and wherein the second support is a different material than the first support. The die may be flip chip bonded to the substrate and the underfill may secure the die to the substrate. The first support may be attached to the substrate using an adhesive and the second support may be attached to the first support using an adhesive.

公开(公告)号：US20180263117A1

公开(公告)日：2018-09-13

申请号：US15810800

申请日：2017-11-13

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravindranath V. Mahajan ,  James C. Matayabas, JR. ,  Johanna M. Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H01L23/00

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US20150262968A1

公开(公告)日：2015-09-17

申请号：US14727205

申请日：2015-06-01

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Ravindranath V Mahajan ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/677

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/67709 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/15 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2221/68309 ,  H01L2221/68313 ,  H01L2221/68331 ,  H01L2221/68363 ,  H01L2224/04105 ,  H01L2224/2101 ,  H01L2224/2919 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/8312 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.

Abstract translation: 本说明书的主题涉及用于在多芯片封装内精确地集成微电子管芯的方法，其基本上减少或消除了在整合过程期间由微电子管芯的移动引起的任何不对准。 这些方法可以包括使用临时粘合剂与具有用于微电子管芯对准的至少一个凹部的载体的使用，使用用于微电子管芯对准的精密模制载体，在可重复使用的载体上使用微电子骰子的磁对准， 和/或在可重复使用的载体上使用具有模制工艺的临时粘合剂。

公开(公告)号：US09076882B2

公开(公告)日：2015-07-07

申请号：US13908016

申请日：2013-06-03

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Ravindranath V Mahajan ,  Omkar Karhade ,  Nitin Deshpande

IPC: H01L21/00 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/67709 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/15 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L2221/68309 ,  H01L2221/68313 ,  H01L2221/68331 ,  H01L2221/68363 ,  H01L2224/04105 ,  H01L2224/2101 ,  H01L2224/2919 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/8312 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The subject matter of the present description relates to methods for the precise integration of microelectronic dice within a multichip package which substantially reduce or eliminate any misalign caused by the movement of the microelectronic dice during the integration process. These methods may include the use of a temporary adhesive in conjunction with a carrier having at least one recess for microelectronic die alignment, the use of a precision molded carrier for microelectronic die alignment, the use of magnetic alignment of microelectronic dice on a reusable carrier, and/or the use of a temporary adhesive with molding processes on a reusable carrier.

Abstract translation: 本说明书的主题涉及用于在多芯片封装内精确地集成微电子管芯的方法，其基本上减少或消除了在整合过程期间由微电子管芯的移动引起的任何不对准。 这些方法可以包括使用临时粘合剂与具有用于微电子管芯对准的至少一个凹部的载体的使用，使用用于微电子管芯对准的精密模制载体，在可重复使用的载体上使用微电子骰子的磁对准， 和/或在可重复使用的载体上使用具有模制工艺的临时粘合剂。