公开(公告)号：US09189296B2

公开(公告)日：2015-11-17

申请号：US14142137

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Bahaa Fahim ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

IPC: G06F15/00 ,  G06F9/52 ,  G06F12/08

CPC classification number: G06F9/524 ,  G06F12/0815 ,  G06F12/0855

Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.

Abstract translation: 这里公开了一种用于防止处理器中的死锁的缓存代理。 缓存代理包括被配置为从处理器的核心接收请求的接收器。 缓存代理包括耦合到接收器的入口逻辑，以确定请求潜在地是可缓存的请求。 入口逻辑是确定请求不会耗尽可用的一致性资源。 入口逻辑是允许响应于该请求不消耗可用的一致性资源的确定来处理该请求。

公开(公告)号：US11860670B2

公开(公告)日：2024-01-02

申请号：US17553458

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Monam Agarwal ,  Anand K. Enamandram ,  Wei Chen ,  Kerry Vander Kamp ,  Robert A. Branch ,  Yen-Cheng Liu

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0292 ,  G06F12/0238 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/1668 ,  G06F2212/1021

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

公开(公告)号：US11734174B2

公开(公告)日：2023-08-22

申请号：US16576687

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Tejpal Singh ,  Yen-Cheng Liu ,  Lavanya Subramanian ,  Mahesh Kumashikar ,  Sri Harsha Choday ,  Sreenivas Subramoney ,  Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0806 ,  G06F11/20

CPC classification number: G06F12/0804 ,  G06F11/2089 ,  G06F12/0806 ,  G06F12/0866

Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

公开(公告)号：US11586579B2

公开(公告)日：2023-02-21

申请号：US17513795

申请日：2021-10-28

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z. Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/04 ,  G06F1/12 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20220114122A1

公开(公告)日：2022-04-14

申请号：US17556853

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US11269793B2

公开(公告)日：2022-03-08

申请号：US16937499

申请日：2020-07-23

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L45/74 ,  G06F8/73 ,  H04L12/46

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20210089448A1

公开(公告)日：2021-03-25

申请号：US16576687

申请日：2019-09-19

Applicant: Intel Corporation

Inventor： Huichu Liu ,  Tanay Karnik ,  Tejpal Singh ,  Yen-Cheng Liu ,  Lavanya Subramanian ,  Mahesh Kumashikar ,  Sri Harsha Chodav ,  Sreenivas Subramoney ,  Kaushik Vaidyanathan ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G06F12/0804 ,  G06F11/20 ,  G06F12/0806 ,  G06F12/0866

Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes—first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is “primary” and other is called the “assist”. Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.

公开(公告)号：US20190205139A1

公开(公告)日：2019-07-04

申请号：US15858899

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

IPC: G06F9/30

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

公开(公告)号：US20190102295A1

公开(公告)日：2019-04-04

申请号：US15721121

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Samantika S. Sury ,  Robert G. Blankenship ,  Simon C. Steely, JR. ,  Yen-Cheng Liu

IPC: G06F12/084 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/0811

Abstract: A method for adaptively performing a set of data transfer processes in a multi-core processor is described. The method may include receiving, by a shared cache from a first core cache, a first request for a cache line; determining, by the shared cache in response to receipt of the first request, whether the cache line is a widely-shared cache line or a single-producer-single-consumer cache line; and performing, by the first core cache and a second core cache, a three-hop data transfer process in response to determining that the cache line is a single-producer-single-consumer cache line, wherein the three-hop data transfer process transfers the cache line directly from the second core cache to the first core cache.

公开(公告)号：US20180373633A1

公开(公告)日：2018-12-27

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.