公开(公告)号：US20200058771A1

公开(公告)日：2020-02-20

申请号：US16103289

申请日：2018-08-14

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  ChoongHyun Lee ,  Shogo Mochizuki

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L21/02 ,  H01L21/225 ,  H01L29/78

Abstract: A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions.

公开(公告)号：US20200020539A1

公开(公告)日：2020-01-16

申请号：US16582315

申请日：2019-09-25

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Hemanth Jagannathan ,  ChoongHyun Lee ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/84 ,  H01L29/49 ,  H01L21/02 ,  H01L29/161 ,  H01L29/51

Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

公开(公告)号：US20190393100A1

公开(公告)日：2019-12-26

申请号：US16017352

申请日：2018-06-25

Applicant: International Business Machines Corporation

Inventor： ChoongHyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/8238 ,  H01L21/285 ,  H01L29/66 ,  H01L23/535 ,  H01L27/092 ,  H01L29/45 ,  H01L29/78 ,  H01L29/08

Abstract: A method for manufacturing a vertical transistor device includes respectively forming a first and second plurality of fins in first and second device regions on a substrate. A plurality of bottom source/drain regions are formed adjacent lower portions of each of the fins, and a sacrificial layer is formed in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions. In the method, gate structures are formed on the bottom source/drain regions and sacrificial layer, and portions of the gate structures are removed to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region. The method further includes depositing a germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region, and converting the germanium oxide layer to a plurality of silicide/germanide layers.

公开(公告)号：US10439044B1

公开(公告)日：2019-10-08

申请号：US15954843

申请日：2018-04-17

Applicant: International Business Machines Corporation

Inventor： ChoongHyun Lee ,  Kangguo Cheng ,  Juntao Li ,  Peng Xu

IPC: H01L21/02 ,  H01L29/10 ,  H01L21/332 ,  H01L29/66 ,  H01L29/161 ,  H01L21/306 ,  H01L29/78 ,  H01L21/308 ,  H01L21/324 ,  H01L21/225

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer having a first concentration of germanium on a semiconductor substrate, a second semiconductor layer having a second concentration of germanium on the first semiconductor layer, and a third semiconductor layer having a third concentration of germanium on the second semiconductor layer. The method also includes patterning the first, second and third semiconductor layers into at least one fin, and reducing a width of the second semiconductor layer of the at least one fin. In the method, a bottom source/drain region is grown from the substrate adjacent a base portion of the at least one fin, a gate structure is formed on and around the second semiconductor layer, and a top source/drain region is grown from the third semiconductor layer.

公开(公告)号：US10395989B2

公开(公告)日：2019-08-27

申请号：US15788469

申请日：2017-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

Abstract: A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.

公开(公告)号：US10326001B2

公开(公告)日：2019-06-18

申请号：US15692294

申请日：2017-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robinhsinku Chao ,  ChoongHyun Lee ,  Heng Wu ,  Chun W. Yeung ,  Jingyun Zhang

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor devices and methods of forming the same include forming a layer of activating material on sidewalls of a stack of alternating layers of channel material and sacrificial material. The layer of activating material is annealed to cause the activating material to react with the sacrificial material and to form insulating spacers at ends of the layers of sacrificial material. The layer of activating material is etched away to expose ends of the layers of channel material. Source/drain regions are formed on the ends of the layers of channel material.

公开(公告)号：US20180337097A1

公开(公告)日：2018-11-22

申请号：US15596629

申请日：2017-05-16

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  ChoongHyun Lee ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L21/324 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/49 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.

公开(公告)号：US20180331096A1

公开(公告)日：2018-11-15

申请号：US15590627

申请日：2017-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee

IPC: H01L27/088 ,  H01L21/324 ,  H01L21/8234 ,  H01L27/098

CPC classification number: H01L27/0886 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/098

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

公开(公告)号：US10079233B2

公开(公告)日：2018-09-18

申请号：US15279154

申请日：2016-09-28

Applicant: International Business Machines Corporation

Inventor： Robin Hsin-Ku Chao ,  Hemanth Jagannathan ,  ChoongHyun Lee ,  Chun Wing Yeung ,  Jingyun Zhang

IPC: H01L21/324 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A method of forming a semiconductor device, includes forming first and second SiGe fins on a substrate, forming a protective layer on the first SiGe fin, forming a germanium-containing layer on the second SiGe fin and on the protective layer on the first SiGe fin, and performing an anneal to react the germanium-containing layer with a surface of the second SiGe fin.

公开(公告)号：US20180212040A1

公开(公告)日：2018-07-26

申请号：US15918199

申请日：2018-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/324 ,  H01L29/423

CPC classification number: H01L29/66553 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/324 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.