公开(公告)号：US20240177918A1

公开(公告)日：2024-05-30

申请号：US18071237

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Mohammad Mamunur RAHMAN

IPC: H01F27/28 ,  H01F27/30 ,  H01F41/04 ,  H01L23/08 ,  H01L23/31

CPC classification number: H01F27/2804 ,  H01F27/306 ,  H01F41/041 ,  H01L23/08 ,  H01L23/3128 ,  H01F2027/2809 ,  H01F2027/2819

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate, a first opening through the core substrate, a second opening through the core substrate and adjacent to the first opening, and a first structure around the core substrate between the first opening and the second opening. In an embodiment, the first structure is electrically conductive. The package core may further comprise a second structure around the core substrate outside of the first opening and the second opening, where the second structure is electrically conductive.

公开(公告)号：US20240063069A1

公开(公告)日：2024-02-22

申请号：US17892930

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Rahul N. MANEPALLI ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Jeremy D. ECTON ,  Gang DUAN ,  Suddhasattwa NAD

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/15

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/15 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates with glass cores. In an embodiment, a core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass, In an embodiment, through glass vias (TGVs) pass through the substrate, and notches are formed into the first surface and the second surface of the substrate.

公开(公告)号：US20240006297A1

公开(公告)日：2024-01-04

申请号：US17853582

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Darko GRUJICIC ,  Marcel WALL ,  Yi YANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L23/538 ,  H01L21/481

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric. Embodiments allow an unroughened surface for the copper feature to reduce the insertion loss for transmission lines that go through the unroughened surface of the copper. Embodiments may include sequential interlayers between a dielectric and copper. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006283A1

公开(公告)日：2024-01-04

申请号：US17853487

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattawa NAD ,  Rahul N. MANEPALLI ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Yi YANG ,  Marcel WALL ,  Darko GRUJICIC ,  Haobo CHEN ,  Aaron GARELICK

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L2224/16225 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming such substrates. In an embodiment, a package substrate comprises a core, a first layer over the core, where the first layer comprises a metal, and a second layer over the first layer, where the second layer comprises an electrical insulator. In an embodiment, the package substrate further comprises a third layer over the second layer, where the third layer comprises a dielectric material, and where an edge of the core extends past edges of the first layer, the second layer, and the third layer.

公开(公告)号：US20230420375A1

公开(公告)日：2023-12-28

申请号：US18367285

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek IBRAHIM ,  Kristof DARMAWIKARTA ,  Rahul N. MANEPALLI ,  Debendra MALLIK ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/09 ,  H01L25/0652

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20230326866A1

公开(公告)日：2023-10-12

申请号：US18208785

申请日：2023-06-12

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Sri Ranga Sai BOYAPATI ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Javier SOTO GONZALEZ ,  Kwangmo LIM

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/00 ,  H01L24/06 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2924/18162 ,  H01L2224/18

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.

公开(公告)号：US20230093438A1

公开(公告)日：2023-03-23

申请号：US17481266

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Bai NIE ,  Tarek A. IBRAHIM ,  Ankur AGRAWAL ,  Sandeep GAAN ,  Ravindranath V. MAHAJAN ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H04B10/70 ,  G02B6/124 ,  G02B6/13

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises a mold material. In an embodiment, a first photonics integrated circuit (PIC) is within the second layer. In an embodiment, a second PIC is within the second layer, and a waveguide is in the first layer. In an embodiment, the waveguide optically couples the first PIC to the second PIC.

公开(公告)号：US20230083222A1

公开(公告)日：2023-03-16

申请号：US17476357

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Hari MAHALINGAM ,  Bai NIE

IPC: G02B6/122 ,  G02B6/13

Abstract: Embodiments disclosed herein include electronic packages with photonics integrated circuits (PICs). In an embodiment, an electronic package comprises a glass substrate with a first recess and a second recess. In an embodiment, a PIC is in the first recess. In an embodiment, an optics module is in the second recess, and an optical waveguide is embedded in the glass substrate between the first recess and the second recess. In an embodiment, the optical waveguide optically couples the PIC to the optics module.

公开(公告)号：US20230057384A1

公开(公告)日：2023-02-23

申请号：US17408157

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Hiroki TANAKA ,  Jason M. GAMBA ,  Srinivas V. PIETAMBARAM

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments disclosed herein include carriers and methods of using the carriers to assemble electronic packages. In an embodiment, a carrier for electronic packaging assembly comprises a mold layer with a first surface and a second surface. In an embodiment, a plurality of glass substrates are embedded in the mold layer. In an embodiment, individual ones of the glass substrates comprise a third surface and a fourth surface, where the third surface of the glass substrate is substantially coplanar with the first surface of the mold layer.

公开(公告)号：US20220278032A1

公开(公告)日：2022-09-01

申请号：US17186289

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Debendra MALLIK ,  Kristof DARMAWIKARTA ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.