公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20240321656A1

公开(公告)日：2024-09-26

申请号：US18126134

申请日：2023-03-24

Applicant: Intel Corporation

Inventor： Gang DUAN ,  Aaron GARELICK ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM

IPC: H01L23/15 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass, and an insert in the core. In an embodiment, the insert is a different material than the core. In an embodiment, a first layer is over the core and a second layer is under the core. In an embodiment, a notch is provided through the first layer, the core, and the second layer. In an embodiment, the notch passes through the insert in the core.

公开(公告)号：US20240213156A1

公开(公告)日：2024-06-27

申请号：US18089491

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Tarek A. IBRAHIM ,  Aaron GARELICK ,  Srikant NEKKANTY ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/53209 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/642 ,  H01L24/05 ,  H01L24/29 ,  H01L25/0655 ,  H01L2224/04026 ,  H01L2224/05567 ,  H01L2224/29007 ,  H01L2224/29021 ,  H01L2224/29101 ,  H01L2924/1436 ,  H01L2924/15321

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core and buildup layers over the core. In an embodiment, a pad is provided on the buildup layers. In an embodiment, a liquid metal well is over the pad.

公开(公告)号：US20240006283A1

公开(公告)日：2024-01-04

申请号：US17853487

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattawa NAD ,  Rahul N. MANEPALLI ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Yi YANG ,  Marcel WALL ,  Darko GRUJICIC ,  Haobo CHEN ,  Aaron GARELICK

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L2224/16225 ,  H01L24/16

Abstract: Embodiments disclosed herein include package substrates and methods of forming such substrates. In an embodiment, a package substrate comprises a core, a first layer over the core, where the first layer comprises a metal, and a second layer over the first layer, where the second layer comprises an electrical insulator. In an embodiment, the package substrate further comprises a third layer over the second layer, where the third layer comprises a dielectric material, and where an edge of the core extends past edges of the first layer, the second layer, and the third layer.