公开(公告)号：US10396086B2

公开(公告)日：2019-08-27

申请号：US15639733

申请日：2017-06-30

申请人： Young-Hwan Son ,  Jae-Hoon Jang ,  Jee-Hoon Han

发明人： Young-Hwan Son ,  Jae-Hoon Jang ,  Jee-Hoon Han

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11573

摘要： A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

公开(公告)号：US08563378B2

公开(公告)日：2013-10-22

申请号：US13238104

申请日：2011-09-21

申请人： Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

发明人： Jae-Joo Shim ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sang-Yong Park

IPC分类号： H01L21/336

CPC分类号： H01L29/7831 ,  H01L27/11582 ,  H01L29/7926

摘要： A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.

摘要翻译： 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。

公开(公告)号：US08222742B2

公开(公告)日：2012-07-17

申请号：US12457290

申请日：2009-06-05

申请人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

IPC分类号： H01L23/48

CPC分类号： H01L27/11519 ,  H01L23/481 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

摘要翻译： 半导体器件包括具有第一导电区域并且包括至少一个虚设第一导电区域的下半导体层，在下半导体层上具有第二导电区域的上半导体层，并且包括至少一个虚拟第二导电区域， 上半导体层并且穿过虚设第二导电区域和虚设第二导电区域下的上半导体层，在下半导体层上的下导电线并且电连接到第一导电区域，在上半导体层上的上导电线， 电连接到第二导电区域，以及在下导电线路和上导电线路之间的穿透孔中的第一导电插塞，第一导电插头电连接下导电线路和上导电线路并与穿孔的侧壁间隔开 。

公开(公告)号：US10199116B2

公开(公告)日：2019-02-05

申请号：US15664303

申请日：2017-07-31

申请人： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

发明人： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US08846421B2

公开(公告)日：2014-09-30

申请号：US13416202

申请日：2012-03-09

申请人： Jin-Woo Lee ,  Jae-Hoon Jang ,  Dong-Hoon Lee ,  Jae-Ha Kim

发明人： Jin-Woo Lee ,  Jae-Hoon Jang ,  Dong-Hoon Lee ,  Jae-Ha Kim

IPC分类号： H01L21/00 ,  H01L33/62 ,  H01L33/60

CPC分类号： H01L33/62 ,  H01L33/60 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/8592 ,  H01L2924/181 ,  H01L2933/0066 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A method of manufacturing a lead frame for a light-emitting device package and a light-emitting device package are provided. The method of manufacturing a lead frame for a light-emitting device package includes: preparing a base substrate for the lead frame; forming diffusion roughness on the base substrate; and forming a reflective plating layer on the diffusion roughness formed base substrate.

摘要翻译： 提供一种制造发光器件封装引线框和发光器件封装的方法。 制造发光器件封装的引线框架的方法包括：准备用于引线框架的基底基板; 在基底基板上形成扩散粗糙度; 在扩散粗糙化基底上形成反射镀层。

公开(公告)号：US20090315187A1

公开(公告)日：2009-12-24

申请号：US12457290

申请日：2009-06-05

申请人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Han-Soo Kim ,  Jae-Hoon Jang

IPC分类号： H01L23/522

CPC分类号： H01L27/11519 ,  H01L23/481 ,  H01L27/11524 ,  H01L27/11551 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a lower semiconductor layer with first conductive regions and including at least one dummy first conductive region, an upper semiconductor layer with second conductive regions on the lower semiconductor layer and including at least one dummy second conductive region, a penetration hole in the upper semiconductor layer and penetrating the dummy second conductive region and the upper semiconductor layer under the dummy second conductive region, a lower conductive line on the lower semiconductor layer and electrically connected to the first conductive regions, an upper conductive line on the upper semiconductor layer and electrically connected to the second conductive regions, and a first conductive plug in the penetration hole between the lower conductive line and the upper conductive line, the first conductive plug electrically connecting the lower and upper conductive lines and being spaced apart from sidewalls of the penetration hole.

摘要翻译： 半导体器件包括具有第一导电区域并且包括至少一个虚设第一导电区域的下半导体层，在下半导体层上具有第二导电区域的上半导体层，并且包括至少一个虚拟第二导电区域， 上半导体层并且穿过虚设第二导电区域和虚设第二导电区域下的上半导体层，在下半导体层上的下导电线并且电连接到第一导电区域，在上半导体层上的上导电线， 电连接到第二导电区域，以及在下导电线路和上导电线路之间的穿透孔中的第一导电插塞，第一导电插头电连接下导电线路和上导电线路并与穿孔的侧壁间隔开 。

公开(公告)号：US09747995B2

公开(公告)日：2017-08-29

申请号：US15176269

申请日：2016-06-08

申请人： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

发明人： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US08923053B2

公开(公告)日：2014-12-30

申请号：US14029100

申请日：2013-09-17

申请人： Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jae-Hoon Jang ,  Byoungkeun Son

发明人： Jinman Han ,  Sunil Shim ,  Hansoo Kim ,  Jae-Hoon Jang ,  Byoungkeun Son

IPC分类号： G11C16/04 ,  G11C16/34 ,  H01L27/115 ,  G11C16/16 ,  G11C16/10 ,  H01L29/792

CPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a method of operating a nonvolatile memory device that includes a substrate and memory blocks having a plurality of memory cells stacked along a direction perpendicular to the substrate. The method includes: reading data from a selected sub block among sub blocks of a selected memory block and selectively refreshing each sub block of the selected memory block in response to the reading of the selected sub block, wherein each sub block of the selected memory block is separately erased.

摘要翻译： 提供了一种操作包括基板的非易失性存储器件的方法和具有沿着垂直于衬底的方向堆叠的多个存储单元的存储器块。 该方法包括：响应于所选择的子块的读取，从所选择的存储器块的子块中读取选定的子块的数据并选择刷新所选存储块的每个子块，其中所选存储块的每个子块 被单独擦除。

公开(公告)号：US08772857B2

公开(公告)日：2014-07-08

申请号：US13221380

申请日：2011-08-30

申请人： Byeong-In Choe ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Han-Soo Kim ,  Jin-Man Han

发明人： Byeong-In Choe ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Han-Soo Kim ,  Jin-Man Han

IPC分类号： H01L29/788

CPC分类号： H01L27/11582 ,  H01L29/7926

摘要： A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.

摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线和字符串选择线（SSL）。 通道沿基本上垂直于基板的顶表面的第一方向延伸，并且通道的厚度根据高度而不同。 GSL，字线和SSL顺序地形成在通道的第一方向的侧壁上并且彼此间隔开。

公开(公告)号：US20100001337A1

公开(公告)日：2010-01-07

申请号：US12456537

申请日：2009-06-18

申请人： Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

发明人： Han-Soo Kim ,  Jae-Hoon Jang ,  Hoo-Sung Cho

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L27/11551 ,  H01L27/0207 ,  H01L27/0688

摘要： A semiconductor memory device includes: sequentially stacked first and second semiconductor layers; at least one first memory transistor disposed on the first semiconductor layer; and at least one second memory transistor disposed on the second semiconductor layer, wherein a gate electrode of the first memory transistor has a broader width than that of the second memory transistor.

摘要翻译： 半导体存储器件包括：顺序堆叠的第一和第二半导体层; 设置在所述第一半导体层上的至少一个第一存储晶体管; 以及设置在所述第二半导体层上的至少一个第二存储晶体管，其中所述第一存储晶体管的栅电极具有比所述第二存储晶体管宽的宽度。