公开(公告)号：US20050178657A1

公开(公告)日：2005-08-18

申请号：US11099066

申请日：2005-04-05

申请人： Kyle Kirby ,  Warren Farnworth

发明人： Kyle Kirby ,  Warren Farnworth

IPC分类号： H01L21/288 ,  H01L21/768 ,  H01L23/48 ,  C25D1/00 ,  C25D5/38 ,  H01L21/44

CPC分类号： H01L21/2885 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  Y10S438/928 ,  H01L2924/014

摘要： Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate. The at least one via is closed at one end by a conductive element forming a conductive structure of the semiconductor substrate. The backside of the semiconductor substrate is exposed to an electroplating solution containing a conductive material in solution with the active surface semiconductor substrate isolated therefrom. An electric potential is applied across the conductive element through the electroplating solution and a conductive contact pad in direct or indirect electrical communication with the conductive element at the closed end of the at least one via (or forming such conductive element) to cause conductive material to electrochemically deposit from the electroplating solution and fill the at least one via. Semiconductor devices and in-process semiconductor devices are also disclosed.

摘要翻译： 用导电材料填充高纵横比孔的方法。 在半导体衬底的背面形成至少一个高宽比通孔。 至少一个通孔在一端由形成半导体衬底的导电结构的导电元件封闭。 将半导体衬底的背面暴露于含有与其分离的活性表面半导体衬底的溶液中的导电材料的电镀溶液。 电导通过电镀溶液施加在导电元件上，导电接触焊盘在至少一个通孔的封闭端（或形成这种导电元件）与导电元件直接或间接电连通，以使导电材料 从电镀溶液电化学沉积并填充至少一个通孔。 还公开了半导体器件和工艺中半导体器件。

公开(公告)号：US20050116351A1

公开(公告)日：2005-06-02

申请号：US11031160

申请日：2005-01-06

申请人： Kyle Kirby ,  Warren Farnworth

发明人： Kyle Kirby ,  Warren Farnworth

IPC分类号： G01R1/067 ,  H01L23/48 ,  H01L23/498 ,  H05K3/32 ,  H05K3/40

CPC分类号： G01R1/06733 ,  B33Y70/00 ,  B33Y80/00 ,  G01R1/06711 ,  G01R1/07314 ,  G01R3/00 ,  H01L23/49811 ,  H01L24/72 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/326 ,  H05K3/4092 ,  H01L2924/00 ,  H01L2224/05599

摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.

摘要翻译： 用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。 每个互连触点包括形成为导电弹簧元件的柔性导电层。 此外，投诉导电层包括用于接合部件触点的尖端和用于弹性地支撑尖端的弹簧部分部分。 一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。 成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。 导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。 互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

公开(公告)号：US20070045858A1

公开(公告)日：2007-03-01

申请号：US11218243

申请日：2005-09-01

申请人： Kyle Kirby ,  William Hiatt ,  Richard Stocks

发明人： Kyle Kirby ,  William Hiatt ,  Richard Stocks

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/76868 ,  H01L21/76873 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.

摘要翻译： 在微型工件中形成互连的方法以及具有这种互连的微型工件在此公开。 在一个实施例中，在微特征工件中形成互连的方法包括：将通过端子和电介质层延伸的孔形成在工件的衬底中的至少中间深度。 该孔在电介质层中具有第一横向尺寸，并且该基板中的第二横向尺寸靠近介电层和基底之间的界面。 第二横向尺寸大于第一横向尺寸。 该方法还包括在孔的至少一部分中与端子电接触地构造导电互连。

公开(公告)号：US20060043512A1

公开(公告)日：2006-03-02

申请号：US10925406

申请日：2004-08-24

申请人： Steven Oliver ,  James Wark ,  Kyle Kirby

发明人： Steven Oliver ,  James Wark ,  Kyle Kirby

IPC分类号： H01L31/0232

CPC分类号： H04N5/2254 ,  B33Y80/00 ,  G02B7/006 ,  G02B7/022 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14685 ,  H01L31/02325 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15174 ,  H04N5/2253 ,  H01L2924/00014

摘要： Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed herein. In one embodiment, the imager assembly can include a workpiece with a substrate having a front side, a back side, and a plurality of imaging dies on and/or in the substrate. The imaging dies include image sensors, integrated circuitry operatively coupled to the image sensors, and external contacts electrically coupled to the integrated circuitry. The assembly also includes optics supports on the workpiece. The optics supports have openings aligned with corresponding image sensors and first interface features at reference locations relative to corresponding image sensors. The assembly further includes optical devices having optics elements and second interface features seated with corresponding first interface features to position the optics elements at a desired location relative to corresponding image sensors.

摘要翻译： 本文公开了具有整体参考特征的光学装置的微电子成像器组件和用于组装这种微电子成像器的方法。 在一个实施例中，成像器组件可以包括具有衬底的工件，其具有在衬底上和/或衬底中的前侧，后侧和多个成像管芯。 成像管芯包括图像传感器，可操作地耦合到图像传感器的集成电路以及电耦合到集成电路的外部触点。 组件还包括工件上的光学支架。 光学支架具有与对应的图像传感器对准的开口和相对于相应图像传感器的参考位置处的第一界面特征。 组件还包括具有光学元件的光学装置和与对应的第一界面特征相对的第二界面特征，以将光学元件相对于相应的图像传感器定位在期望的位置。

公开(公告)号：US20050275049A1

公开(公告)日：2005-12-15

申请号：US10864974

申请日：2004-06-10

申请人： Kyle Kirby ,  Salman Akram ,  William Hiatt

发明人： Kyle Kirby ,  Salman Akram ,  William Hiatt

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L27/146 ,  H01L31/0203 ,  H01L31/0232

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L27/14618 ,  H01L27/14625 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H04N5/2257 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending partially through the substrate to the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, a conductive layer deposited onto at least a portion of the dielectric liner, a wetting agent deposited onto at least a portion of the conductive layer, and a conductive fill material deposited into the passage and electrically coupled to the bond-pad.

摘要翻译： 本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。 在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。 接合焊盘由衬底承载并电耦合到集成电路。 导电晶片互连部分地穿过衬底延伸并与焊盘接触。 互连可以包括部分地延伸穿过衬底到接合焊盘的通道，沉积到通道中并与衬底接触的介电衬垫，沉积在电介质衬垫的至少一部分上的导电层，沉积在电介质衬垫上的润湿剂 所述导电层的至少一部分以及沉积到所述通道中并电耦合到所述接合焊盘的导电填充材料。

公开(公告)号：US20050127478A1

公开(公告)日：2005-06-16

申请号：US10733226

申请日：2003-12-10

申请人： William Hiatt ,  Kyle Kirby

发明人： William Hiatt ,  Kyle Kirby

IPC分类号： H01L21/68 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L29/40

CPC分类号： H01L24/14 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.

摘要翻译： 本文公开了用于在微特征工件和模具中填充通孔并形成导电互连的微电子器件和方法。 在一个实施例中，一种方法包括提供具有多个模具的微特征工件和从微特征工件的第一侧延伸穿过微特征工件的至少一个通道到微特征工件的相对的第二侧。 该方法还可以包括在邻近微电子工件的第一侧的通道中形成导电插塞，以及在通道中沉积导电材料，以至少大体上填充从导电插头到微电子工件的第二侧的通道。

公开(公告)号：US20070267754A1

公开(公告)日：2007-11-22

申请号：US11832742

申请日：2007-08-02

申请人： Kyle Kirby ,  William Hiatt ,  Richard Stocks

发明人： Kyle Kirby ,  William Hiatt ,  Richard Stocks

IPC分类号： H01L23/528

CPC分类号： H01L21/76898 ,  H01L21/76868 ,  H01L21/76873 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.

摘要翻译： 在微型工件中形成互连的方法以及具有这种互连的微型工件在此公开。 在一个实施例中，在微特征工件中形成互连的方法包括：将通过端子和电介质层延伸的孔形成在工件的衬底中的至少中间深度。 该孔在电介质层中具有第一横向尺寸，并且该基板中的第二横向尺寸靠近介电层和基底之间的界面。 第二横向尺寸大于第一横向尺寸。 该方法还包括在孔的至少一部分中与端子电接触地构造导电互连。

公开(公告)号：US20060177999A1

公开(公告)日：2006-08-10

申请号：US11056211

申请日：2005-02-10

申请人： David Hembree ,  Charles Watkins ,  Kyle Kirby ,  Steven Oliver ,  Salman Akram ,  Sidney Rigg

发明人： David Hembree ,  Charles Watkins ,  Kyle Kirby ,  Steven Oliver ,  Salman Akram ,  Sidney Rigg

IPC分类号： H01L21/44

CPC分类号： H01L21/76898

摘要： Methods for forming interconnects in blind holes and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the invention is directed toward a method for manufacturing a microelectronic workpiece having microelectronic dies with integrated circuits and terminals electrically coupled to the integrated circuits. In one embodiment, the method includes forming a blind hole in the workpiece. The blind hole extends from a first exterior side of the workpiece to an intermediate depth in the workpiece. The method continues by forming a vent in the workpiece. The vent is in fluid communication with the blind hole. The method further includes constructing an electrically conductive interconnect in at least a portion of the blind hole.

摘要翻译： 在这里公开了在盲孔中形成互连件的方法和具有这种互连的微电子工件的方法。 本发明的一个方面涉及一种用于制造微电子工件的方法，所述微电子工件具有集成电路和与集成电路电连接的端子的微电子管芯。 在一个实施例中，该方法包括在工件中形成盲孔。 盲孔从工件的第一外侧延伸到工件的中间深度。 该方法通过在工件中形成通气来继续。 排气口与盲孔流体连通。 该方法还包括在盲孔的至少一部分中构造导电互连。

公开(公告)号：US20060042952A1

公开(公告)日：2006-03-02

申请号：US10925501

申请日：2004-08-24

申请人： Steven Oliver ,  Kyle Kirby ,  William Hiatt

发明人： Steven Oliver ,  Kyle Kirby ,  William Hiatt

IPC分类号： C25D5/02 ,  H05K3/00

CPC分类号： H01L21/76898

摘要： Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed by first removing the bulk of the material from portions of the back side of the workpiece without thinning the entire workpiece. The bulk removal process, for example, can form a first opening that extends to an intermediate depth within the workpiece, but does not extend to the contact surface of the electrically conductive element. After forming the first opening, a second opening is formed from the intermediate depth in the first opening to the contact surface of the conductive element. The second opening has a second width less than the first width of the first opening. This method further includes filling the blind vias with a conductive material and subsequently thinning the workpiece from the exterior side until the cavity is eliminated.

摘要翻译： 用于在盲孔或其它类型的孔中形成互连的方法，以及具有这种互连的微电子工件。 盲孔可以通过首先从工件的后侧的部分去除大部分材料而不使整个工件变薄来形成。 散装移除过程例如可以形成延伸到工件内的中间深度但不延伸到导电元件的接触表面的第一开口。 在形成第一开口之后，从第一开口的中间深度到导电元件的接触表面形成第二开口。 第二开口具有小于第一开口的第一宽度的第二宽度。 该方法还包括用导电材料填充盲孔，随后从外侧使工件变薄直到空腔被消除。

公开(公告)号：US20080020505A1

公开(公告)日：2008-01-24

申请号：US11863087

申请日：2007-09-27

申请人： Salman Akram ,  Charles Watkins ,  Kyle Kirby ,  Alan Wood ,  Wiliam Hiatt

发明人： Salman Akram ,  Charles Watkins ,  Kyle Kirby ,  Alan Wood ,  Wiliam Hiatt

IPC分类号： H01L21/00

CPC分类号： H01L27/146 ,  H01L21/76898 ,  H01L27/14618 ,  H01L27/148 ,  H01L31/02016 ,  H01L2224/48227 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/00

摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.

摘要翻译： 本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。 在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。 接合焊盘由衬底承载并电耦合到集成电路。 导电晶片互连延伸穿过衬底并与接合焊盘接触。 互连可以包括完全延伸穿过衬底和接合焊盘的通道，沉积到通道中并与衬底接触的电介质衬垫，沉积在电介质衬垫的至少一部分上的第一和第二导电层以及导电 在第二导电层的至少一部分上沉积到通道中并且电耦合到接合焊盘的填充材料。