公开(公告)号：US09595334B2

公开(公告)日：2017-03-14

申请号：US15163927

申请日：2016-05-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C16/10 ,  G06F12/02 ,  G11C16/34 ,  G11C11/56 ,  G11C15/04 ,  G11C16/04 ,  G06F7/02 ,  G11C16/26 ,  G11C16/12 ,  G11C16/14

CPC classification number: G11C16/10 ,  G06F7/02 ,  G06F12/0246 ,  G06F2207/00 ,  G06F2207/025 ,  G11C11/56 ,  G11C11/5628 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatus and methods of operating a memory include storing a value of an attribute of a feature vector to a pair of memory cells by programming each of the memory cells to a respective data state of three or more data states, searching for an exact match to a particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells only when the value of the attribute is the particular value, and searching for an inexact match to the particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells when the value of the attribute is within a range of possible values of the attribute including the particular value.

Abstract translation: 操作存储器的装置和方法包括通过将每个存储器单元编程为三个或更多数据状态的相应数据状态来将特征向量的属性的值存储到一对存储器单元，搜索与 通过将属性的各个电压电平施加到控制存储器单元的栅极以仅仅在属性的值是特定值才激活两个存储器单元，并通过应用相应的值来搜索与特定值的不精确匹配的属性的特定值 当属性的值在包括特定值的属性的可能值的范围内时，控制存储器单元的栅极的电压电平来激活两个存储器单元。

公开(公告)号：US20160267993A1

公开(公告)日：2016-09-15

申请号：US15163927

申请日：2016-05-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/10 ,  G06F7/02 ,  G06F12/0246 ,  G06F2207/00 ,  G06F2207/025 ,  G11C11/56 ,  G11C11/5628 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatus and methods of operating a memory include storing a value of an attribute of a feature vector to a pair of memory cells by programming each of the memory cells to a respective data state of three or more data states, searching for an exact match to a particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells only when the value of the attribute is the particular value, and searching for an inexact match to the particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells when the value of the attribute is within a range of possible values of the attribute including the particular value.

Abstract translation: 操作存储器的装置和方法包括通过将每个存储器单元编程为三个或更多数据状态的相应数据状态来将特征向量的属性的值存储到一对存储器单元，搜索与 通过将属性的各个电压电平施加到控制存储器单元的栅极以仅仅在属性的值是特定值才激活两个存储器单元，并通过应用相应的值来搜索与特定值的不精确匹配的属性的特定值 当属性的值在包括特定值的属性的可能值的范围内时，控制存储器单元的栅极的电压电平来激活两个存储器单元。

公开(公告)号：US20160231930A1

公开(公告)日：2016-08-11

申请号：US15098574

申请日：2016-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Luigi Pilolli

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0875 ,  G06F12/0893 ,  G06F13/1668 ,  G06F2212/2022 ,  G06F2212/452 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/16 ,  G11C11/4074 ,  G11C11/4096 ,  G11C16/06 ,  G11C16/10 ,  G11C2207/2245 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.

Abstract translation: 用于操作存储器设备中的分布式控制器系统的方法包括接收读取命令，主控制器响应于读取命令向数据高速缓存控制器生成指示，并且数据高速缓存控制器从存储器设备的存储器阵列接收数据 响应指示。

公开(公告)号：US20150318047A1

公开(公告)日：2015-11-05

申请号：US14798845

申请日：2015-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C16/04

CPC classification number: G11C16/28 ,  G11C15/00 ,  G11C15/046 ,  G11C16/0483

Abstract: Memory devices and methods are disclosed. One such method compares input data to stored data in a memory device and includes applying a first weight factor to a first string of memory cells coupled to a data line, where a first bit of the stored data is stored in the first string of memory cells; applying a second weight factor to a second string of memory cells coupled to the data line, where a second bit of the stored data is stored in the second string of memory cells; comparing a first bit of input data to the first bit of the stored data while the first weight factor is applied to the first string of memory cells; and comparing a second bit of the input data to the second bit of the stored data while the second weight factor is applied to the second string of memory cells.

Abstract translation: 公开了存储器件和方法。 一种这样的方法将输入数据与存储器件中的存储数据进行比较，并且包括将第一加权因子应用于耦合到数据线的存储器单元的第一串，其中存储的数据的第一位被存储在第一存储单元串中 ; 将第二加权因子应用于耦合到所述数据线的第二存储单元串，其中存储数据的第二位存储在所述第二存储单元串中; 将第一加权因子应用于第一串存储器单元时，将第一比特的输入数据与存储数据的第一比较; 以及将所述输入数据的第二位与存储的数据的第二位进行比较，同时将所述第二权重因子应用于所述第二存储单元串。

公开(公告)号：US20140156904A1

公开(公告)日：2014-06-05

申请号：US14170728

申请日：2014-02-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Pasquale Conenna

IPC: G06F13/16

CPC classification number: G06F12/0246 ,  G06F12/0875 ,  G06F13/16 ,  G06F13/1694 ,  G06F2212/202 ,  G06F2212/452 ,  G11C16/10

Abstract: A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit.

Abstract translation: 总线控制器具有置换器，耦合到置换器的算术逻辑单元和选择性地耦合到置换器和算术逻辑单元的替换器。

公开(公告)号：US11875859B2

公开(公告)日：2024-01-16

申请号：US17189529

申请日：2021-03-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04

CPC classification number: G11C16/28 ,  G11C15/00 ,  G11C15/046 ,  G11C16/0483

Abstract: A memory device might include control circuitry configured to cause the memory device to compare input data to data stored in memory cells connected to a data line, cause a first level of current to flow from the data line in response to a mismatch between one digit of the input data and data stored in a respective pair of memory cells, cause a second level of current to flow from the data line in response to a mismatch between a different digit of the input data and the data stored in a respective pair of memory cells, compare a representation of a level of current in the data line to a reference, and deem the input data to potentially match or not match the data stored in the plurality of memory cells in response to the comparison.

公开(公告)号：US11775185B2

公开(公告)日：2023-10-03

申请号：US16948426

申请日：2020-09-17

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Walter Di Francesco ,  Yuanhang Cao ,  Luca De Santis ,  Fumin Gu

IPC: G06F3/06 ,  G06F9/50

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679 ,  G06F9/505 ,  G06F9/5094 ,  G06F2209/5018

Abstract: A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and control logic. The control logic comprises a plurality of processing threads to execute memory access operations on the memory array concurrently, a thread selection component to identify one or more processing threads of the plurality of processing threads for a power management cycle of the associated memory die and a power management component to determine an amount of power associated with the one or more processing threads and request the amount of power during the power management cycle.

公开(公告)号：US11551758B2

公开(公告)日：2023-01-10

申请号：US17206827

申请日：2021-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26

Abstract: Memories might include control logic configured to cause the memory to perform a first sense operation having an initial phase and a plurality of sensing phases on a first grouping of memory cells, pause the first sense operation upon completion of a present sensing phase in response to receiving a command to perform a second sense operation on a second grouping of memory cells while performing the present sensing phase, perform an initial phase of the second sense operation after pausing the first sense operation, and, in response to completion of the initial phase of the second sense operation, resume the first sense operation at a next subsequent sensing phase of the plurality of sensing phases and continue to a sensing phase of the second sense operation to perform the next subsequent sensing phase of the first sense operation and the sensing phase of the second sense operation concurrently.

公开(公告)号：US20210383876A1

公开(公告)日：2021-12-09

申请号：US17408774

申请日：2021-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C11/56 ,  G06F11/07 ,  G11C29/02

Abstract: Memory having a controller configured to cause the memory to determine a respective raw data value of a plurality of possible raw data values for each memory cell of a plurality of memory cells, count occurrences of each raw data value for a first set of memory cells of the plurality of memory cells, store a cumulative number of occurrences for each raw data value, determine a plurality of valleys of the stored cumulative number of occurrences for each raw data value with each valley corresponding to a respective raw data value of the plurality of possible raw data values, and, for each memory cell of a second set of memory cells of the plurality of memory cells, determine a data value for that memory cell in response to the raw data value for that memory cell and the respective raw data values of the plurality of valleys.

公开(公告)号：US11062785B2

公开(公告)日：2021-07-13

申请号：US16839304

申请日：2020-04-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Apparatus including an array of memory cells, a plurality of access lines each corresponding to a respective plurality of memory cells of the array of memory cells and each connected to a control gate of each memory cell of its respective plurality of memory cells; and a controller for access of the array of memory cells that is configured to cause the apparatus to apply a particular voltage level to a particular access line of the plurality of access lines, and determine a value indicative of a number of memory cells of the respective plurality of memory cells for the particular access line that are activated in response to applying the particular voltage level. The controller might further be configured to determine an expected data age of the respective plurality of memory cells, and/or determine a plurality of read voltages for reading the respective plurality of memory cells.