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61.发明申请公开(公告)号：US20190213073A1
公开(公告)日：2019-07-11
申请号：US16352530
申请日：2019-03-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Patrick R. Khayat , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Mark A. Helm , Aaron S. Yip
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/08 , G11C7/08 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C29/52 , G11C2029/0411 , G11C2211/5641 , H03M13/1111 , H03M13/1177 , H03M13/2909 , H03M13/3723 , H03M13/612
Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.
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62.发明授权公开(公告)号：US10289484B2
公开(公告)日：2019-05-14
申请号：US15267844
申请日：2016-09-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Patrick R. Khayat , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Mark A. Helm , Aaron S. Yip
IPC: G06F11/00 , G06F11/10 , G06F3/06 , G11C16/08 , G11C16/26 , G11C29/52 , H03M13/11 , H03M13/37 , H03M13/00 , G11C29/04 , H03M13/29
Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.
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公开(公告)号：US20180308551A1
公开(公告)日：2018-10-25
申请号：US15928856
申请日：2018-03-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Mark A. Helm , Kalyan C. Kavalipurapu
CPC classification number: G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/3459
Abstract: Methods of operating a memory include boosting a channel voltage of a memory cell selected for programming to a particular voltage level for a particular programming pulse, boosting the channel voltage of the memory cell selected for programming to a second voltage level, greater than the particular voltage level, for a subsequent programming pulse, and boosting the channel voltage of the memory cell selected for programming to a third voltage level, greater than the second voltage level, for a next subsequent programming pulse.
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公开(公告)号：US10014061B1
公开(公告)日：2018-07-03
申请号：US15484369
申请日：2017-04-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Aaron S. Yip , Mark A. Helm
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459
Abstract: Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each of the strings of series-connected memory cells is selectively connected to the same data line through a respective plurality of select gates connected in series between that string and the data line. One select gate of each of the pluralities of select gates has a threshold voltage within a first range of threshold voltages, and each remaining select gate of each of the pluralities of select gates has a threshold voltage within a second range of threshold voltages mutually exclusive from the first range of threshold voltages. Each of the select gates having a threshold voltage within the first range of threshold voltages has its control gate isolated from any of the other select gates having a threshold voltage within the first range of threshold voltages.
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公开(公告)号：US09552888B2
公开(公告)日：2017-01-24
申请号：US14724065
申请日：2015-05-28
Applicant: Micron Technology, Inc.
Inventor： Mark A. Helm , Uday Chandrasekhar
CPC classification number: G11C16/28 , G06F11/10 , G06F11/1008 , G06F11/1068 , G11C16/3454 , G11C29/52 , H03M13/03 , H03M13/05
Abstract: Methods and devices for data sensing are disclosed. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.
Abstract translation: 公开了用于数据感测的方法和装置。 一种这样的方法包括使用多个不同感测电压对多个存储器单元执行多个连续感测操作，确定在连续感测操作的数量的连续感测操作之间改变状态的数量存储器单元的数量，以及确定 至少部分地基于确定在连续感测操作之间改变状态的存储器单元的数量的确定数量，是否输出对应于多个连续感测操作中的一个的硬数据。
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Patent Agency Ranking
公开(公告)号：US09251908B2
公开(公告)日：2016-02-02
申请号：US14227295
申请日：2014-03-27
Applicant: Micron Technology, Inc.
Inventor： Uday Chandrasekhar , Mark A. Helm
CPC classification number: G11C16/3427 , G11C16/04 , G11C16/10 , G11C16/3454
Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
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67.发明申请MEMORY DEVICES WITH LOCAL AND GLOBAL DEVICES AT SUBSTANTIALLY THE SAME LEVEL ABOVE STACKED TIERS OF MEMORY CELLS AND METHODS 有权具有本地和全球设备的存储器件大部分位于存储器单元的堆叠层和方法上公开(公告)号：US20150279432A1
公开(公告)日：2015-10-01
申请号：US14735350
申请日：2015-06-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Aaron S. Yip , Mark A. Helm , Ramin Ghodsi
CPC classification number: G11C5/025 , G11C5/063 , G11C8/08 , G11C11/06035 , G11C11/06064 , G11C11/063 , G11C16/02 , G11C16/0483 , H01L27/11531 , H01L27/11573 , Y10T29/49069
Abstract: In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices.
Abstract translation: 在一个实施例中，存储器设备包括层级的存储器单元的堆叠，位于存储器单元的层级之上的层级的本地设备层，以及与本地设备层基本相同的级别的全球设备层 。 本地设备可以提供对数据线的选择性访问。 全局设备可以提供对全局接入线的选择性访问。 一层存储器单元可以由全球设备层的全局设备选择性地耦合到全局接入线路。
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公开(公告)号：US08780626B2
公开(公告)日：2014-07-15
申请号：US13762559
申请日：2013-02-08
Applicant: Micron Technology, Inc.
Inventor： Yijie Zhao , Akira Goda , Mark A. Helm
CPC classification number: G11C16/04 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418 , G11C16/3422 , G11C2211/5641
Abstract: Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.
Abstract translation: 公开了用于感测和存储器件的方法。 一种用于感测的方法确定与要感测的m位存储器单元相邻的n位存储器单元的阈值电压。 要感测的m位存储器单元的控制栅极利用响应于所确定的n位存储单元的阈值电压而调整的感测电压进行偏置。
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公开(公告)号：US08711615B2
公开(公告)日：2014-04-29
申请号：US13938078
申请日：2013-07-09
Applicant: Micron Technology, Inc.
Inventor： Uday Chandrasekhar , Mark A. Helm
IPC: G11C11/34
Abstract: This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
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公开(公告)号：US11640262B2
公开(公告)日：2023-05-02
申请号：US16868868
申请日：2020-05-07
Applicant: Micron Technology, Inc.
Inventor： Mark A. Helm
Abstract: Systems and methods are disclosed including a memory component and a processing device, coupled to the memory component. The processing device can program a block of the memory component using a first type of memory cells storing a first number of bits per memory cell. The processing device can then determine that an amount of memory used of the memory component is greater than a capacity threshold. Responsive to determining that a frequency of access to the block meets a criterion, the processing device can then program the block using a second type memory cells storing a second number of bits per memory cell, wherein the second number of bits exceeds the first number of bits.
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