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    FUNCTIONAL DATA PROGRAMMING IN A NON-VOLATILE MEMORY
    63.
    发明申请
    FUNCTIONAL DATA PROGRAMMING IN A NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20170206967A1

    公开(公告)日：2017-07-20

    申请号：US15479520

    申请日：2017-04-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ramin Ghodsi

    IPC: G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G06F11/1008 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/349

    Abstract: Methods of operating a memory include receiving a plurality of digits of data, determining a value of the plurality of digits of data, and selecting a function to represent the value of the plurality of digits of data. The selected function is a function of a cell number of each memory cell within a grouping of memory cells. The methods further include determining a desired threshold voltage of a particular memory cell of the grouping of memory cells corresponding to the value of the selected function for the cell number of the particular memory cell, and programming the particular memory cell to its desired threshold voltage.

    APPARATUSES AND METHODS FOR REDUCING READ DISTURB
    65.
    发明申请
    APPARATUSES AND METHODS FOR REDUCING READ DISTURB 审中-公开

    公开(公告)号：US20170162269A1

    公开(公告)日：2017-06-08

    申请号：US15436289

    申请日：2017-02-17

    Applicant: Micron Technology, Inc.

    Inventor： Feng Pan ,  Ramin Ghodsi ,  Qiang Tang

    IPC: G11C16/34 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26

    Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.

    LADDER-BASED HIGH SPEED SWITCH REGULATOR
    66.
    发明申请
    LADDER-BASED HIGH SPEED SWITCH REGULATOR 有权
    基于梯形图的高速开关稳压器

    公开(公告)号：US20160181915A1

    公开(公告)日：2016-06-23

    申请号：US14581710

    申请日：2014-12-23

    Applicant: Micron Technology, Inc.

    Inventor： Feng Pan ,  Ramin Ghodsi

    IPC: H02M3/156

    CPC classification number: H02M3/156 ,  G05F1/59

    Abstract: Some embodiments include apparatuses having a switch regulator that includes a first circuit with a first comparator to compare an output of the switch regulator to a first reference voltage, and to provide a control signal to enable or disable a first pass element based on the comparison. The switch regulator includes at least a second circuit having a second comparator to compare an output of the switch regulator to a second reference voltage that is lower than the first reference voltage, and to provide a control signal to enable or disable a second pass element based on the comparison. The switch regulator does not include Miller compensation circuits. Other apparatuses and methods according to other embodiments are described.

    Abstract translation: 一些实施例包括具有开关调节器的装置，该开关调节器包括具有第一比较器的第一电路，用于将开关调节器的输出与第一参考电压进行比较，并且基于该比较来提供控制信号以启用或禁用第一通过元件。 开关调节器至少包括具有第二比较器的第二电路，用于将开关调节器的输出与低于第一参考电压的第二参考电压进行比较，并且提供控制信号以使第二通过元件基于 比较。 开关稳压器不包括米勒补偿电路。 描述根据其他实施例的其他装置和方法。

    High-input common-mode differential amplifiers
    67.
    发明授权
    High-input common-mode differential amplifiers 有权
    高输入共模差分放大器

    公开(公告)号：US09337776B1

    公开(公告)日：2016-05-10

    申请号：US14581682

    申请日：2014-12-23

    Applicant: Micron Technology, Inc.

    Inventor： Feng Pan ,  Ramin Ghodsi

    IPC: G11C5/14 ,  H03F1/02 ,  H03F3/45

    CPC classification number: H03F1/0205 ,  G11C5/145 ,  G11C7/062 ,  H03F3/45183 ,  H03F3/45632 ,  H03F2203/45081 ,  H03F2203/45482 ,  H03F2203/45674

    Abstract: The present invention discloses a level-shifting circuit to provide an initial stage to a differential amplifier circuit, a differential amplifier circuit, and a method of operating same. An example level-shifting circuit includes a first transistor and a second transistor to receive a first differential amplifier input. The first transistor has a drain receiving a power input, and the second transistor has a drain coupled to a source of the first transistor and a source coupled to a biased tail circuit. The example level-shifting circuit further includes a third transistor and a fourth transistor to receive a second differential amplifier input. The third transistor has a drain receiving a power input and the fourth transistor has a drain coupled to a source of the third transistor and a source coupled to the biased tail circuit. Other examples, methods, and apparatuses are described herein.

    Abstract translation: 本发明公开了一种向差分放大电路提供初始级的电平移位电路，差分放大电路及其操作方法。 示例电平移位电路包括用于接收第一差分放大器输入的第一晶体管和第二晶体管。 第一晶体管具有接收功率输入的漏极，并且第二晶体管具有耦合到第一晶体管的源极的漏极和耦合到偏置尾部电路的源极。 示例电平移位电路还包括第三晶体管和第四晶体管，以接收第二差分放大器输入。 第三晶体管具有接收功率输入的漏极，并且第四晶体管具有耦合到第三晶体管的源极的漏极和耦合到偏置尾部电路的源极。 本文描述了其它示例，方法和装置。

    THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION
    68.
    发明申请
    THRESHOLD VOLTAGE DISTRIBUTION DETERMINATION 有权
    阈值电压分配确定

    公开(公告)号：US20160099048A1

    公开(公告)日：2016-04-07

    申请号：US14868604

    申请日：2015-09-29

    Applicant: Micron Technology, Inc.

    Inventor： Qiang Tang ,  Feng Pan ,  Ramin Ghodsi ,  Mark A. Helm

    IPC: G11C11/56

    CPC classification number: G11C11/5642 ,  G11C7/14 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409

    Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.

    Abstract translation: 描述了用于阈值电压（Vt）分布测定的装置和方法。 许多设备可以包括感测电路，其被配置为确定存储器单元阵列的源极线上的第一电流，第一电流对应于响应于第一感测而导通的一组存储器单元的第一数量的存储器单元 施加到访问线路的电压并确定源极线路上的第二电流，第二电流对应于响应于施加到接入线路的第二感测电压而导通的组中的第二数量的存储器单元。 设备的数量可以包括控制器，其被配置为至少部分地基于第一电流和第二电流来确定对应于该组存储器单元的Vt分布的至少一部分。

    Apparatuses and methods and for providing power responsive to a power loss
    69.
    发明授权
    Apparatuses and methods and for providing power responsive to a power loss 有权
    装置和方法，并且用于响应于功率损耗提供功率

    公开(公告)号：US09213386B2

    公开(公告)日：2015-12-15

    申请号：US13657444

    申请日：2012-10-22

    Applicant: Micron Technology, Inc.

    Inventor： Ramin Ghodsi

    IPC: G06F1/32 ,  G06F11/30 ,  G06F1/30 ,  G06F13/16

    CPC classification number: G06F1/30 ,  G06F1/3203 ,  G06F1/3268 ,  G06F13/1694

    Abstract: Apparatuses and methods for providing power responsive a power loss are disclosed herein. A power chip may comprise a power sensor, a write command control logic, and an array. The power sensor may be configured to detect a power loss of a power supply and provide a power loss control signal responsive, at least in part, to detecting the power loss of the power supply. The write command control logic may be coupled to the power sensor and may be configured to receive the power loss control signal. The write command control logic may be further configured to provide a write command responsive, at least in part, to receipt of the power loss control signal. The array may include a plurality of capacitors configured to store power and further configured to provide power during the power loss.

    Abstract translation: 本文公开了用于提供响应于功率损耗的功率的装置和方法。 功率芯片可以包括功率传感器，写命令控制逻辑和阵列。 功率传感器可以被配置为检测电源的功率损耗并且至少部分地响应于检测电源的功率损耗而提供功率损耗控制信号。 写命令控制逻辑可以耦合到功率传感器，并且可以被配置为接收功率损耗控制信号。 写命令控制逻辑还可以被配置为至少部分地响应于接收到功率损耗控制信号来提供写入命令。 阵列可以包括被配置为存储电力并被进一步配置成在功率损耗期间提供功率的多个电容器。

    Health scan for content addressable memory
    70.
    发明授权
    Health scan for content addressable memory 有权

    公开(公告)号：US12142334B2

    公开(公告)日：2024-11-12

    申请号：US17729973

    申请日：2022-04-26

    Applicant: Micron Technology, Inc.

    Inventor： Tomoko Ogura Iwasaki ,  Manik Advani ,  Ramin Ghodsi

    IPC: G11C15/04 ,  G11C29/12 ,  G11C29/20 ,  G11C29/42

    Abstract: A memory device includes a content addressable memory (CAM) block storing a plurality of stored search keys. The memory device further includes control logic that determines a first number of memory cells in at least one string of the CAM block storing one of the plurality of stored search keys, the first number of memory cells storing a first logical value, and stores a calculated parity value representing the first number of memory cells in a page cache associated with the CAM block. The control logic further reads stored parity data from one or more memory cells in the at least one string, the one or more memory cells connected to one or more additional wordlines in the CAM block, and compares the calculated parity value to the stored parity data to determine whether an error is present in the one of the plurality of stored search keys in the CAM block.

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