公开(公告)号：US20170352724A1

公开(公告)日：2017-12-07

申请号：US14445942

申请日：2014-07-29

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/861 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0611 ,  H01L21/26586 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0873 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8611

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

公开(公告)号：US09716152B2

公开(公告)日：2017-07-25

申请号：US15245172

申请日：2016-08-23

Applicant: ROHM CO., LTD. ,  MaxPower Semiconductor, Inc.

Inventor： Masaki Nagata ,  Shigenari Okada ,  Mohamed Darwish ,  Jun Zeng ,  Peter Su

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/407 ,  H01L29/0623 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device according to the present invention includes a semiconductor layer having a trench, a first insulating film formed along an inner surface of the trench, and an upper electrode and a lower electrode embedded in the trench via the first insulating film and disposed above and below a second insulating film. An electric field relaxation portion that relaxes an electric field arising between the upper electrode and the semiconductor layer is provided between a side surface of the trench and a lower end portion of the upper electrode.

公开(公告)号：US20160365848A1

公开(公告)日：2016-12-15

申请号：US15182558

申请日：2016-06-14

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H03K17/041 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/78624 ,  H03K17/04106

Abstract: Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended.

Abstract translation: 侧向功率器件，其中静电静电电荷放置在与漂移区相邻的电介质材料中。 屏蔽栅极介于栅电极和漏极之间，以减少米勒电荷。 在一些实施例中，栅电极是沟槽栅极，并且在这种情况下，屏蔽电极也优选地垂直延伸。

公开(公告)号：US09461127B2

公开(公告)日：2016-10-04

申请号：US14873103

申请日：2015-10-01

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/40 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.

公开(公告)号：US20160027880A1

公开(公告)日：2016-01-28

申请号：US14873103

申请日：2015-10-01

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/40 ,  H01L29/423 ,  H01L29/10 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/407 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.

公开(公告)号：US09076861B2

公开(公告)日：2015-07-07

申请号：US14202471

申请日：2014-03-10

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/872 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7806 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/872

Abstract: Power devices which include trench Schottky barrier diodes and also (preferably) trench-gate transistors. Isolation trenches flank both the gate regions and the diode mesas, and have an additional diffusion below the bottom of the isolation trenches. The additional diffusion helps to reduce the electric field (and leakage), when the device is in the OFF state, at both the Schottky barrier and at the body diode.

Abstract translation: 功率器件包括沟道肖特基势垒二极管和（优选）沟槽栅极晶体管。 隔离沟槽面对栅极区域和二极管台面两侧，并且在隔离沟槽底部具有另外的扩散。 当器件处于OFF状态时，附加扩散有助于在肖特基势垒和二极管二极管的同时减小电场（和泄漏）。

公开(公告)号：US09024379B2

公开(公告)日：2015-05-05

申请号：US13758689

申请日：2013-02-04

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/66734 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7835

Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Abstract translation: 用于在单个芯片上集成多个沟槽晶体管的功率半导体器件的方法和系统。 多个功率晶体管（或有源区）并联，但一个晶体管具有较低的阈值电压。 当晶体管正向偏置时，这降低了电压降。 在替代实施例中，具有较低阈值电压的功率器件简单地连接为耗尽二极管，从而分流有源晶体管的体二极管，而不会影响导通和导通状态。

公开(公告)号：US20140117441A1

公开(公告)日：2014-05-01

申请号：US13660622

申请日：2012-10-25

Applicant: MaxPower Semiconductor, Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish

IPC: H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/7802 ,  H01L29/7813

Abstract: Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling.

Abstract translation: 垂直功率器件，包括绝缘沟槽，包含绝缘材料和栅电极，以及相关方法。 定位体区域，使得栅电极上的电压偏置将在体区域中引起反转层。 在沟槽的侧壁处或其附近的永久电荷层在关闭状态期间为耗尽的半导体材料中的空间电荷提供电荷平衡。 导电屏蔽层位于绝缘材料中的栅电极下方，并且减小栅极与沟槽下部之间的电容耦合。 这样可以减少开关损耗。 在其他实施例中，平面栅极电极控制沿着沟槽的垂直传导路径的水平载流子注入，而屏蔽板位于沟槽本身上以减小电容耦合。

公开(公告)号：US20140117367A1

公开(公告)日：2014-05-01

申请号：US13660630

申请日：2012-10-25

Applicant: MaxPower Semiconductor. Inc.

Inventor： Richard A. Blanchard ,  Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/739

CPC classification number: H01L29/7395 ,  H01L21/2255 ,  H01L21/2257 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/408 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7813

Abstract: Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region.

Abstract translation: IGBT等的器件，结构和相关方法，其包括在源体结处的自对准串联电阻以避免闭锁。 通过使用带电电介质和/或通过使用在与源极区相邻的侧壁处使用提供与源极区相同的导电类型的掺杂剂原子的源的电介质来实现串联电阻。

公开(公告)号：US11888047B2

公开(公告)日：2024-01-30

申请号：US16933890

申请日：2020-07-20

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/36 ,  H01L29/423 ,  H01L29/739

CPC classification number: H01L29/66734 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7835 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66666

Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.