公开(公告)号：US20240379838A1

公开(公告)日：2024-11-14

申请号：US18658910

申请日：2024-05-08

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed Darwish ,  Jun Zeng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: A vertical MOSFET has an N-type SiC drift layer connected to a drain electrode. An overlying Si layer creates an n-N heterojunction at the top of the SiC drift layer. A P-well layer and N+ source regions are formed in the Si layer. Trenched gates are formed in the Si layer that invert the P-well to create a conductive path between the Si source regions and the SiC drift region. JFET channel regions and gate regions are formed in the SiC layer for improving reliability of the MOSFET under reverse voltage conditions and under short circuit conditions. The SiC drift layer results in a higher breakdown voltage, lower on-resistance, and improved thermal conductivity, and the upper Si layer retains its higher channel mobility and stability and high gate drive efficiency.

公开(公告)号：US10720511B2

公开(公告)日：2020-07-21

申请号：US16148578

申请日：2018-10-01

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/36 ,  H01L29/423 ,  H01L29/739

Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US10720510B2

公开(公告)日：2020-07-21

申请号：US15975284

申请日：2018-05-09

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/36 ,  H01L29/423 ,  H01L29/739

Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US10510863B2

公开(公告)日：2019-12-17

申请号：US15676792

申请日：2017-08-14

Applicant: MaxPower Semiconductor, Inc.

Inventor： Richard A. Blanchard ,  Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L21/265 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417

Abstract: In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

公开(公告)号：US10325980B2

公开(公告)日：2019-06-18

申请号：US16014635

申请日：2018-06-21

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/861 ,  H01L29/66 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

公开(公告)号：US10157983B2

公开(公告)日：2018-12-18

申请号：US15894811

申请日：2018-02-12

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Wenfang Du ,  Richard A. Blanchard ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L29/739 ,  H01L29/40

Abstract: In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.

公开(公告)号：US20180358449A1

公开(公告)日：2018-12-13

申请号：US15620547

申请日：2017-06-12

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish

IPC: H01L29/66 ,  H01L21/04 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L21/02

CPC classification number: H01L29/66734 ,  H01L21/02164 ,  H01L21/02249 ,  H01L21/02332 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/7397 ,  H01L29/7813

Abstract: A silicon carbide (or comparable) trench transistor in which gate dielectric anneal, in an oxynitriding atmosphere, is performed after all other high-temperature steps have already been done.

公开(公告)号：US10014404B2

公开(公告)日：2018-07-03

申请号：US14603181

申请日：2015-01-22

Applicant: MaxPower Semiconductor, Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/49 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4975 ,  H01L29/7811 ,  H01L29/7813

Abstract: MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances.

公开(公告)号：US20180138293A1

公开(公告)日：2018-05-17

申请号：US15809863

申请日：2017-11-10

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L29/739 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/417 ,  H01L29/40 ,  H01L29/36 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/66734 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/7835

Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

公开(公告)号：US20170330962A1

公开(公告)日：2017-11-16

申请号：US15663465

申请日：2017-07-28

Applicant: MaxPower Semiconductor Inc.

Inventor： Jun Zeng ,  Mohamed N. Darwish ,  Kui Pu ,  Shih-Tzung Su

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

Abstract: In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.