公开(公告)号：US20190109081A1

公开(公告)日：2019-04-11

申请号：US16200873

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/48

Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

公开(公告)号：US20190109079A1

公开(公告)日：2019-04-11

申请号：US15730272

申请日：2017-10-11

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jack E. Murray

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768

Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.

公开(公告)号：US20180342476A1

公开(公告)日：2018-11-29

申请号：US15603327

申请日：2017-05-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Benjamin L. McClain

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/18

Abstract: A semiconductor device assembly is provided. The assembly includes a first package element and a second package element disposed over the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface-mounted to the first package element and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad. The first height is about equal to a sum of the solder joint thickness and the second height.

公开(公告)号：US20160172242A1

公开(公告)日：2016-06-16

申请号：US15050858

申请日：2016-02-23

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

公开(公告)号：US09299663B2

公开(公告)日：2016-03-29

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/04 ,  H01L23/544 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。

公开(公告)号：US20150333014A1

公开(公告)日：2015-11-19

申请号：US14281362

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

Abstract translation: 这里描述了微电子器件和制造方法的各种实施例。 在一个实施例中，用于将电子特征对准到贯通基板通孔的方法包括形成具有围绕TSV的至少一部分的壁的自对准对准特征，并将光刻工具对准自对准对准特征。 在一些实施例中，自对准对准特征由设备背面的种子材料的形貌定义。

公开(公告)号：US12251841B2

公开(公告)日：2025-03-18

申请号：US18409692

申请日：2024-01-10

Applicant: Micron Technology, Inc.

Inventor： Kuan Wei Tseng ,  Brandon P. Wirz

IPC: B25J9/16 ,  B25J13/08 ,  B25J19/02 ,  H01L21/67 ,  H01L23/00 ,  H05K13/08

Abstract: An apparatus for handling microelectronic devices comprises a pick arm having a pick surface configured for receiving a microelectronic device thereon, drives for moving the pick arm and reorienting the pick surface in the X, Y and Z planes and about a horizontal rotational axis and a vertical rotational axis, and a sensor device carried by the pick arm and configured to detect at least one of at least one magnitude of force and at least one location of force applied between the pick surface and a structure contacted by the pick surface or a structure and a microelectronic device carried on the pick surface.

公开(公告)号：US12100661B2

公开(公告)日：2024-09-24

申请号：US18368987

申请日：2023-09-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/53238 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50

Abstract: Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

公开(公告)号：US12087720B2

公开(公告)日：2024-09-10

申请号：US17198144

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Benjamin L. McClain

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L24/14 ,  H01L24/02 ,  H01L24/04 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/50 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05561 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06517 ,  H01L2224/13007 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14517 ,  H01L2224/16013 ,  H01L2224/16059 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/3511 ,  H01L2224/94 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/81

Abstract: A semiconductor device assembly is provided. The assembly includes a first package element and a second package element disposed over the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface-mounted to the first package element and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad. The first height is about equal to a sum of the solder joint thickness and the second height.

公开(公告)号：US12087697B2

公开(公告)日：2024-09-10

申请号：US18214378

申请日：2023-06-26

Applicant: Micron Technology, Inc.

Inventor： Ruei Ying Sheng ,  Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/50 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/50 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L25/0657

Abstract: Semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. Each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. The semiconductor dies can be directly coupled to each other via the insulating material. The semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. The interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. The interconnect structure can also include a plurality of protrusions extending from the monolithic via. Each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.