公开(公告)号：US20140289574A1

公开(公告)日：2014-09-25

申请号：US14353401

申请日：2012-10-19

Applicant: RAMBUS INC.

Inventor： Ely Tsern ,  Frederick A. Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24

CPC classification number: G06F11/1008 ,  G11C5/04 ,  G11C29/24 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

Abstract translation: 公开了一种在集成电路（IC）存储器件中的操作方法。 该方法包括以第一刷新率刷新IC存储设备中的第一组存储行。 测试每行的保留时间。 对被测试给定行的测试包括以比第一刷新率慢的第二刷新率刷新。 测试可以基于存储在给定行中的数据的访问请求而中断。

公开(公告)号：US12111723B2

公开(公告)日：2024-10-08

申请号：US18233250

申请日：2023-08-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G11C7/10 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  H03M13/15 ,  G06F11/20

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  H03M13/1575 ,  G06F11/20 ,  G11C2029/4402 ,  G11C29/765

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

公开(公告)号：US20240104036A1

公开(公告)日：2024-03-28

申请号：US18482268

申请日：2023-10-06

Applicant: Rambus Inc

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10

CPC classification number: G06F13/287 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G06F2213/28

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US20240020249A1

公开(公告)日：2024-01-18

申请号：US18365696

申请日：2023-08-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Craig E. Hampel ,  Scott C. Best ,  John Yan

IPC: G06F13/16

CPC classification number: G06F13/1678 ,  G06F13/1673 ,  G06F13/1694

Abstract: Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.

公开(公告)号：US20230307026A1

公开(公告)日：2023-09-28

申请号：US18094908

申请日：2023-01-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt

IPC: G11C11/00 ,  G11C5/04 ,  G11C5/06 ,  G06F3/06 ,  G06F11/10 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C11/005 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1076 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/12

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.

公开(公告)号：US11556433B2

公开(公告)日：2023-01-17

申请号：US17321053

申请日：2021-05-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  J. James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G11C7/20 ,  G11C14/00 ,  G06F3/06

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

公开(公告)号：US11341070B2

公开(公告)日：2022-05-24

申请号：US17100560

申请日：2020-11-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  G11C5/02

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US20210173800A1

公开(公告)日：2021-06-10

申请号：US17100560

申请日：2020-11-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G11C7/10 ,  G11C5/04 ,  G06F13/16

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US11010263B2

公开(公告)日：2021-05-18

申请号：US16254920

申请日：2019-01-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  J. James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G11C7/20 ,  G11C14/00 ,  G06F3/06

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

公开(公告)号：US20200168288A1

公开(公告)日：2020-05-28

申请号：US16690743

申请日：2019-11-21

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24 ,  G11C29/50 ,  G06F11/10

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.