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144 条记录 (耗时 0.037 秒)

    Programming mode selection with JTAG circuits
    65.
    发明授权
    Programming mode selection with JTAG circuits 有权
    使用JTAG电路进行编程模式选择

    公开(公告)号：US06681378B2

    公开(公告)日：2004-01-20

    申请号：US10175980

    申请日：2002-06-19

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    IPC分类号： G06F1750

    CPC分类号： H03K19/1732 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744 ,  H03K19/17748

    摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).

    摘要翻译： 通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。 具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。 用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。 在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

    Phase-locked loop circuitry for programmable logic devices
    66.
    发明授权
    Phase-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环电路

    公开(公告)号：US06483886B1

    公开(公告)日：2002-11-19

    申请号：US09366940

    申请日：1999-08-04

    申请人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Richard G. Cliff

    发明人： Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Richard G. Cliff

    IPC分类号： H03L706

    CPC分类号： H03K19/1774 ,  H03K19/177 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/183

    摘要： A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.

    摘要翻译： 锁相环电路（“PLL”）可在相位和频率两个方面调节。 通过在PLL的压控振荡器上提供多个抽头，并提供单独的多路复用器，每个复用器可以为PLL反馈回路选择不同的抽头，并为PLL输出选择一个，一个允许用户调整 输出的相位相对于输入的相位。 类似地，通过提供可加载的预缩放（除以N），后标尺（除以K）和反馈量表（除以M）计数器，允许用户将输出的频率调整为M /（NK ）倍的输入。

    Programming mode selection with JTAG circuits
    67.
    发明授权
    Programming mode selection with JTAG circuits 失效
    使用JTAG电路进行编程模式选择

    公开(公告)号：US06421812B1

    公开(公告)日：2002-07-16

    申请号：US09094186

    申请日：1998-06-09

    申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Bonnie Wang ,  Khai Nguyen ,  Richard G. Cliff

    IPC分类号： G06F1750

    CPC分类号： H03K19/1732 ,  G01R31/318555 ,  G06F11/2273 ,  H03K19/17744 ,  H03K19/17748

    摘要： A technique to provide higher system performance by increasing amount of data that may be transferred in parallel is to increase the number of external pins available for the input and output of user data (user I/O). Specifically, a technique is to reduce the number of dedicated pins used for user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction stored in an instruction register (220) may be used to replace the programming mode select pins (252) in a programmable logic device (PLD).

    摘要翻译： 通过增加并行传输的数据量来提供更高系统性能的技术是增加可用于输入和输出用户数据（用户I / O）的外部引脚数。 具体来说，一种技术是减少用于用户I / O的专用引脚数，从而为用户I / O提供更多的外部引脚。 用于实现诸如JTAG边界扫描架构的功能的专用引脚也可用于提供其他功能，例如选择编程模式。 在具体实施例中，也可以使用尚未用于存储在指令寄存器（220）中的JTAG边界扫描指令的JTAG指令代码来替代可编程逻辑器件（PLD）中的编程模式选择引脚（252）。

    Variable depth and width memory device
    69.
    发明授权
    Variable depth and width memory device 失效
    可变深度和宽度的存储设备

    公开(公告)号：US5717901A

    公开(公告)日：1998-02-10

    申请号：US555109

    申请日：1995-11-08

    申请人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff

    发明人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff

    IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F12/00

    CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

    摘要： A programmable variable depth and width random-access memory circuit is provided. The memory circuit contains rows and columns of memory cells for storing data. A row decoder is used to address individual rows of the memory cells. Column address circuitry receives a column address signal and a width and depth selection signal. A column decoder within the column address circuitry addresses one or more columns of memory cells of the RAM array based on the selected width of the array. The output of the column decoder is routed to the appropriate column or columns of memory cells by a pattern of fixed connections and a group of programmable multiplexers. The number of data output lines to which data signals are provided is determined by the selected width of the RAM array. The output circuitry contains a group of programmable demultiplexers and a routing array having a pattern of fixed connections suitable for passing data signals from the RAM array to the selected number of data output lines.

    摘要翻译： 提供了可编程可变深度和宽度随机存取存储器电路。 存储器电路包含用于存储数据的存储单元的行和列。 行解码器用于寻址存储器单元的各行。 列地址电路接收列地址信号和宽度和深度选择信号。 列地址电路中的列解码器基于阵列的选定宽度来寻址RAM阵列的一列或多列存储单元。 列解码器的输出通过固定连接和一组可编程多路复用器的模式路由到存储器单元的适当列或列。 提供数据信号的数据输出线的数量由RAM阵列的选定宽度决定。 输出电路包含一组可编程解复用器和具有适于将数据信号从RAM阵列传递到选定数量的数据输出线的固定连接图案的路由阵列。

    Apparatus for configuring performance of field programmable gate arrays and associated methods
    70.
    发明授权
    Apparatus for configuring performance of field programmable gate arrays and associated methods 有权
    用于配置现场可编程门阵列性能和相关方法的装置

    公开(公告)号：US08461869B1

    公开(公告)日：2013-06-11

    申请号：US13214147

    申请日：2011-08-19

    申请人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

    发明人： Irfan Rahim ,  Andy L. Lee ,  Bruce B. Pedersen ,  Jeffrey T. Watt ,  Mao Du ,  Richard G. Cliff

    IPC分类号： H03K19/003

    CPC分类号： H03K19/003 ,  H03K19/17784

    摘要： An apparatus includes a temperature sensor, a voltage regulator, and a field programmable gate array (FPGA). The temperature sensor and the voltage regulator are adapted, respectively, to provide a temperature signal, and to provide at least one output voltage. The FPGA includes at least one circuit adapted to receive the at least one output voltage of the voltage regulator, and a set of monitor circuits adapted to provide indications of process and temperature for the at least one circuit. The FPGA further includes a controller adapted to derive a body-bias signal and a voltage-level signal from the temperature signal, from the indications of process and temperature for the at least one circuit, and from the at least one output voltage of the voltage regulator. The controller is further adapted to provide the body-bias signal to at least one transistor in the at least one circuit, and to provide the voltage-level signal to the voltage regulator.

    摘要翻译： 一种装置包括温度传感器，电压调节器和现场可编程门阵列（FPGA）。 温度传感器和电压调节器分别适于提供温度信号，并提供至少一个输出电压。 FPGA包括适于接收电压调节器的至少一个输出电压的至少一个电路，以及适于提供至少一个电路的过程和温度指示的一组监视器电路。 FPGA还包括控制器，其适于从温度信号，从至少一个电路的处理和温度指示以及电压的至少一个输出电压导出体偏置信号和电压电平信号 调节器 所述控制器还适于将所述体偏置信号提供给所述至少一个电路中的至少一个晶体管，并且向所述电压调节器提供所述电压电平信号。