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    Method of manufacturing vertical semiconductor device
    62.
    发明授权
    Method of manufacturing vertical semiconductor device 有权
    垂直半导体器件制造方法

    公开(公告)号：US08455316B2

    公开(公告)日：2013-06-04

    申请号：US13325189

    申请日：2011-12-14

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  B82Y10/00 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

    摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

    摘要翻译： 垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分， 所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层， 所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。

    METHOD OF MANUFACTURING A VERTICAL-TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A VERTICAL-TYPE SEMICONDUCTOR DEVICE
    64.
    发明申请
    METHOD OF MANUFACTURING A VERTICAL-TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A VERTICAL-TYPE SEMICONDUCTOR DEVICE 有权
    制造垂直型半导体器件的方法和操作垂直型半导体器件的方法

    公开(公告)号：US20110211399A1

    公开(公告)日：2011-09-01

    申请号：US13102187

    申请日：2011-05-06

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： G11C7/00 ,  H01L21/336 ,  H01L21/8242

    CPC分类号： H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841

    摘要： In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

    摘要翻译： 在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案， 单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面 晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。 形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。 在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

    Semiconductor Devices Semiconductor Pillars and Method of Fabricating the Same
    65.
    发明申请
    Semiconductor Devices Semiconductor Pillars and Method of Fabricating the Same 有权
    半导体器件半导体支柱及其制造方法

    公开(公告)号：US20110039381A1

    公开(公告)日：2011-02-17

    申请号：US12831577

    申请日：2010-07-07

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7841 ,  H01L21/823431 ,  H01L21/823487 ,  H01L27/10802 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/24 ,  H01L29/42356 ,  H01L29/66272 ,  H01L29/66666 ,  H01L29/7827

    摘要： A semiconductor device includes a trench isolation region provided on a substrate and defining first and second active regions separated from each other. A first semiconductor pillar protruding upward from the first active region is provided. A second semiconductor pillar protruding upward from the second active region is provided. A first gate mask extending to cross over the first and second active regions is provided. The first gate mask surrounds upper sidewalls of the first and second semiconductor pillars. A first gate line formed below the first gate mask, separated from the first and second active regions, and surrounding parts of sidewalls of the first and second semiconductor pillars is provided.

    摘要翻译： 半导体器件包括设置在衬底上并限定彼此分离的第一和第二有源区的沟槽隔离区。 提供从第一有源区向上突出的第一半导体柱。 提供从第二有源区向上突出的第二半导体柱。 提供延伸到跨越第一和第二有源区域的第一栅极掩模。 第一栅极掩模围绕第一和第二半导体柱的上侧壁。 提供了形成在第一栅极掩模下方的与第一和第二有源区分离的第一栅极线以及第一和第二半导体柱的侧壁的周围部分。

    Method of forming a MOSFET on a strained silicon layer
    66.
    发明授权
    Method of forming a MOSFET on a strained silicon layer 有权
    在应变硅层上形成MOSFET的方法

    公开(公告)号：US07799648B2

    公开(公告)日：2010-09-21

    申请号：US12478345

    申请日：2009-06-04

    申请人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

    发明人： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

    IPC分类号： H01L21/336

    CPC分类号： C30B29/06 ,  C30B15/00

    摘要： A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

    摘要翻译： 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

    Vertical-type non-volatile memory device
    68.
    发明申请
    Vertical-type non-volatile memory device 审中-公开
    垂直型非易失性存储器件

    公开(公告)号：US20090321816A1

    公开(公告)日：2009-12-31

    申请号：US12459148

    申请日：2009-06-26

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jun Seo ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jun Seo ,  Jong-Hyuk Kang

    IPC分类号： H01L29/792 ,  H01L27/088

    CPC分类号： H01L27/11551 ,  H01L27/11556

    摘要： In a vertical-type non-volatile memory device, first and second single-crystalline semiconductor pillars are arranged to face each other on a substrate. Each of the first and second single-crystalline semiconductor pillars has a rectangular parallelepiped shape with first, second, third and fourth sidewalls. A first tunnel oxide layer, a first charge storage layer and a first blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the first single-crystalline semiconductor pillar. A second tunnel oxide layer, a second charge storage layer and a second blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the second single-crystalline semiconductor pillar. A word line makes contact with surfaces of both the first and second blocking dielectric layers. The word line is used in common for the first and second single-crystalline semiconductor pillars.

    摘要翻译： 在垂直型非易失性存储器件中，第一和第二单晶半导体柱被布置成在衬底上彼此面对。 第一和第二单晶半导体柱中的每一个具有与第一，第二，第三和第四侧壁的长方体形状。 第一隧道氧化物层，第一电荷存储层和第一阻挡介电层依次层叠在第一单晶半导体柱的第一侧壁的整个表面上。 第二隧道氧化物层，第二电荷存储层和第二阻挡电介质层依次层叠在第二单晶半导体柱的第一侧壁的整个表面上。 字线与第一和第二阻挡电介质层的表面接触。 字线用于第一和第二单晶半导体柱。

    Methods of Fabricating Silicon on Insulator (SOI) Wafers
    69.
    发明申请
    Methods of Fabricating Silicon on Insulator (SOI) Wafers 审中-公开
    在绝缘体（SOI）晶片上制造硅的方法

    公开(公告)号：US20090221133A1

    公开(公告)日：2009-09-03

    申请号：US12370783

    申请日：2009-02-13

    申请人： Seung-Woo Choi ,  Dae-Lok Bae ,  Jong-Wook Lee ,  Yong-Won Cha ,  Pil-Kyu Kang ,  Jung-Ho Kim

    发明人： Seung-Woo Choi ,  Dae-Lok Bae ,  Jong-Wook Lee ,  Yong-Won Cha ,  Pil-Kyu Kang ,  Jung-Ho Kim

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76254

    摘要： Methods of fabricating SOI wafers are provided including providing a donor wafer and forming a hydrogen ion implantation layer in the donor wafer. A circumference portion of one side of the donor wafer is recessed to form a height difference. The one side of the donor wafer and a handle wafer are bonded to form a bonded wafer. The bonded wafer is heat treated to separate the bonded wafer along the hydrogen ion implantation layer.

    摘要翻译： 提供制造SOI晶片的方法包括提供施主晶片并在施主晶片中形成氢离子注入层。 供体晶片的一侧的周边部分被凹入以形成高度差。 供体晶片和处理晶片的一侧被结合以形成接合晶片。 接合的晶片被热处理以沿着氢离子注入层分离键合的晶片。

    Method for fabricating a semiconductor device
    70.
    发明授权
    Method for fabricating a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US07560319B2

    公开(公告)日：2009-07-14

    申请号：US11730262

    申请日：2007-03-30

    申请人： Sung-Kwan Kang ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Yong-Hoon Son

    发明人： Sung-Kwan Kang ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Yong-Hoon Son

    IPC分类号： H01L21/84

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84

    摘要： A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.

    摘要翻译： 一种制造半导体器件的方法包括在单晶硅衬底上形成绝缘层结构，通过蚀刻绝缘层结构的一部分形成包括第一开口的第一绝缘层结构图案， 单晶硅层，并且通过将第一激光束照射到非单晶硅层上而形成单晶硅图案。 该方法还包括通过蚀刻第一绝缘层结构的一部分来形成包括第二开口的第二绝缘层结构图案，用非单晶硅锗层填充第二开口，以及形成单晶硅 - 锗图案，通过将第二激光束照射到非单晶硅 - 锗层上。