公开(公告)号：US09871139B2

公开(公告)日：2018-01-16

申请号：US15342003

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Joon Goo Hong ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial epitaxial gate stressor is deposited on the fin, causing strain in the fin. SD structures are then formed to anchor the ends of the fin, and the sacrificial epitaxial gate stressor is removed.

公开(公告)号：US20170345932A1

公开(公告)日：2017-11-30

申请号：US15342008

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Chris Bowen ,  Kiyotaka Imai ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7869

Abstract: A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is deposited on the fin, and processed, e.g., by plasma doping and annealing, to cause stress in the dummy gate. Deep source drain (SD) recesses are formed, resulting in strain in the channel, and SD structures are formed to anchor the ends of the fin. The dummy gate is then removed.

公开(公告)号：US20170271514A1

公开(公告)日：2017-09-21

申请号：US15340951

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L29/165 ,  H01L29/06 ,  H01L21/3213

CPC classification number: H01L29/7848 ,  H01L21/30604 ,  H01L21/32055 ,  H01L21/32133 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.

公开(公告)号：US09466669B2

公开(公告)日：2016-10-11

申请号：US14683926

申请日：2015-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna Obradovic ,  Rwik Sengupta

IPC: H01L29/66 ,  H01L21/3205 ,  H01L27/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/10 ,  H01L21/0257 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/08 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/423 ,  H01L29/42376

Abstract: A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first fin, a first channel region beneath the first gate electrode structure, and first source and drain regions in the first fin on opposite sides of the first channel region, and a second finFET device including a second fin, a second gate electrode structure on sidewalls and an upper surface of the second fin, a second channel region beneath the second gate electrode structure, and second source and drain regions in the second fin on opposite sides of the second channel region. The second gate electrode structure has a second physical gate length that is substantially the same as a first physical gate length of the first gate electrode structure, and the second finFET device has a second effective channel length that is different from a first effective channel length of the first gate electrode structure.

Abstract translation: 半导体结构包括第一鳍式FET器件，其包括第一鳍片，侧壁上的第一栅极电极结构和第一鳍片的上表面，第一栅电极结构下方的第一沟道区域，第一鳍片中的第一源极和漏极区域 在第一沟道区域的相对侧上，以及第二鳍状FET器件，其包括第二鳍片，侧壁上的第二栅电极结构和第二鳍片的上表面，第二栅电极结构下方的第二沟道区域，以及第二源极和 第二鳍片的漏极区域在第二沟道区域的相对侧上。 第二栅极电极结构具有与第一栅极电极结构的第一物理栅极长度基本相同的第二物理栅极长度，并且第二finFET器件具有与第一栅极电极结构的第一有效沟道长度不同的第二有效沟道长度 第一栅电极结构。

公开(公告)号：US09431492B2

公开(公告)日：2016-08-30

申请号：US14628541

申请日：2015-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L29/45 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L27/12 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L29/41791 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/7848 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuit devices including contacts and methods of forming the same are provided. The devices may include a fin on a substrate, a gate structure on the fin and a source/drain region in the fin at a side of the gate structure. The devices may further include a contact plug covering an uppermost surface of the source/drain region and a sidewall of the gate structure. The contact plug may include an inner portion including a first material and an outer portion including a second material different from the first material. The outer portion may at least partially cover a sidewall of the inner portion, and a portion of the outer portion may be disposed between the sidewall of the gate structure and the sidewall of the inner portion.

Abstract translation: 提供了包括触点的集成电路装置及其形成方法。 器件可以包括衬底上的翅片，翅片上的栅极结构和栅极结构侧的鳍中的源极/漏极区域。 所述装置还可以包括覆盖源极/漏极区域的最上表面和栅极结构的侧壁的接触插塞。 接触插塞可以包括包括第一材料的内部部分和包括不同于第一材料的第二材料的外部部分。 外部部分可以至少部分地覆盖内部部分的侧壁，并且外部部分的一部分可以设置在门结构的侧壁和内部部分的侧壁之间。

公开(公告)号：US20160133745A1

公开(公告)日：2016-05-12

申请号：US14934045

申请日：2015-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L21/768

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/743 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/7848

Abstract: Exemplary embodiments provide methods and systems for fabricating a metal source-drain stressor in a MOS device channel having improved tensile stress. Aspects of exemplary embodiment include forming a recess in source and drain areas; forming a metal contact layer on surfaces of the recess that achieves low contact resistivity; forming a metallic diffusion barrier over the metal contact layer; forming a layer M as an intimate mixture of materials A and B that substantially fills the recess; capping the layer M with a capping layer so that layer M is fully encapsulated and the capping layer prevents diffusion of A and B; and forming a compound AxBy within the layer M via a thermal reaction resulting in a reacted layer M comprising the metal source-drain stressor.

Abstract translation: 示例性实施例提供了在具有改善的拉伸应力的MOS器件通道中制造金属源极 - 漏极应力器的方法和系统。 示例性实施例的方面包括在源极和漏极区域中形成凹部; 在凹陷的表面上形成接触电阻率低的金属接触层; 在金属接触层上形成金属扩散阻挡层; 形成层M作为基本上填充凹部的材料A和B的紧密混合物; 用覆盖层覆盖层M，使得层M被完全封装，并且覆盖层防止A和B的扩散; 以及通过热反应在层M内形成化合物AxBy，导致包含金属源 - 漏应力源的反应层M。

公开(公告)号：US20160111337A1

公开(公告)日：2016-04-21

申请号：US14887484

申请日：2015-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8238 ,  H01L21/306 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/823828 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/22 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/775 ,  H01L29/7847

Abstract: Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

Abstract translation: 示例性实施例提供制造双轴应变纳米片。 示例性实施例的方面包括：生长具有一个或多个周期的外延晶体初始超晶格，每个周期包括至少三个层，活性材料层，第一牺牲材料层和第二牺牲材料层，第一和第二 具有不同材料特性的牺牲材料层; 在一个或多个周期的每一个中，将每个活性材料层放置在第一和第二牺牲材料层之间，其中第一和第二牺牲材料层的晶格常数不同于活性材料层并且在活性物质层中施加双轴应力 材料层; 选择性地蚀刻掉所有的第一牺牲材料层，从而暴露活性材料的一个表面以进行附加处理，同时活性材料层中的双轴应变由第二牺牲材料层保持; 并且选择性地蚀刻掉所有第二牺牲材料层，从而暴露活性材料层的第二表面用于额外的处理。

公开(公告)号：US20160020305A1

公开(公告)日：2016-01-21

申请号：US14593636

申请日：2015-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna Obradovic ,  Robert C. Bowen ,  Dharmendar Reddy Palle ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L29/20 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/205 ,  H01L29/7391

Abstract: A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed.

Abstract translation: 场效应晶体管（FET）包括具有第一和第二层叠半导体沟道层的纳米片堆叠。 第一沟道层限定隧道FET的沟道区，而第二沟道层限定了热离子FET的沟道区。 源极和漏极区域设置在纳米片堆叠的相对侧上，使得第一和第二沟道层在它们之间延伸。 与第一沟道层相邻的源极区域的第一部分和与第二沟道层相邻的源极区域的第二部分具有相反的半导体导电类型。 还讨论了相关的制造和操作方法。

公开(公告)号：US20150364546A1

公开(公告)日：2015-12-17

申请号：US14722402

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Rwik Sengupta

IPC: H01L29/10 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/775

Abstract: A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.

Abstract translation: 包括堆叠的纳米片场效应晶体管（FET）的器件可以包括衬底，衬底上的第一沟道图案，第一沟道图案上的第二沟道图案，被配置为围绕第一沟道图案的部分的栅极和部分 的第二沟道图案和第一沟道图案和第二沟道图案的相对端上的源极/漏极区域。 第一和第二通道图案可以各自包括布置在平行于基板的表面的相应水平平面中的相应的多个纳米片。 纳米片可以在相邻的纳米片之间的水平间隔距离处彼此间隔开。 第二通道图案可以与第一通道图案间隔开距离第一通道图案到第二通道图案的垂直间隔距离大于水平间隔距离。

公开(公告)号：US12230570B2

公开(公告)日：2025-02-18

申请号：US17574073

申请日：2022-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon Goo Hong ,  Kang-ill Seo ,  Mark S. Rodder

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L29/06

Abstract: A method of manufacturing an integrated circuit having buried power rails includes forming a first dielectric layer on an upper surface of a first semiconductor substrate, forming a series of power rail trenches in an upper surface of the first dielectric layer, forming the buried power rails in the series of power rail trenches, forming a second dielectric layer on the upper surface of the first dielectric layer and upper surfaces of the buried power rails, forming a third dielectric layer on a donor wafer, bonding the third dielectric layer to the second dielectric layer, and forming a series of semiconductor devices, vias, and metal interconnects on or in the donor wafer. The buried power rails are encapsulated by the first dielectric layer and the second dielectric layer, and the buried power rails are below the plurality of semiconductor devices.