METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE

    公开(公告)号:US20180138382A1

    公开(公告)日:2018-05-17

    申请号:US15868976

    申请日:2018-01-11

    Abstract: A method for manufacturing a light emitting diode package comprises: arranging a first solder and a second solder between a substrate and a light emitting diode; and subjecting the first solder and the second solder to heat treatment to bond the substrate and the light emitting diode. The heat treatment comprises: increasing the temperature of the first and second solders from room temperature to a temperature Tp; maintaining the temperature Tp; and lowering the temperature Tp. The heating step comprises: a first ramping step of increasing a temperature from room temperature to a temperature TA at a constant speed; a pre-heating step of increasing the temperature from the temperature TA to a temperature TB to impart fluidity to the first and second solders; and a second ramping step of increasing the temperature from the TB to TL at a constant speed.

    WAFER LEVEL LIGHT-EMITTING DIODE ARRAY
    67.
    发明申请

    公开(公告)号:US20180108704A1

    公开(公告)日:2018-04-19

    申请号:US15835326

    申请日:2017-12-07

    Abstract: A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes.

Patent Agency Ranking