公开(公告)号：US20160233243A1

公开(公告)日：2016-08-11

申请号：US15082199

申请日：2016-03-28

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/161 ,  H01L29/165 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device with dual isolation are described. The CMOS device includes an n-type field effect transistor (nFET) region, the nFET region including one or more fins comprised of strained silicon, the one or fins in the nFET region being formed on an insulator. The CMOS device also includes a p-type field effect transistor (pFET) region, the pFET region including one or more fins comprised of silicon (Si) or silicon germanium (SiGe) on epitaxially grown silicon and including a shallow trench isolation (STI) fill to isolate the one or more fins of the pFET region from each other.

公开(公告)号：US20160233241A1

公开(公告)日：2016-08-11

申请号：US14618442

申请日：2015-02-10

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L21/027 ,  H01L21/3105 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device with dual isolation are described. The CMOS device includes an n-type field effect transistor (nFET) region, the nFET region including one or more fins comprised of strained silicon, the one or fins in the nFET region being formed on an insulator. The CMOS device also includes a p-type field effect transistor (pFET) region, the pFET region including one or more fins comprised of silicon (Si) or silicon germanium (SiGe) on epitaxially grown silicon and including a shallow trench isolation (STI) fill to isolate the one or more fins of the pFET region from each other.

Abstract translation: 一种在包括p型场效应晶体管器件（pFET）和n型场效应晶体管（nFET）器件的双隔离互补金属氧化物半导体（CMOS）器件中形成鳍片的方法和具有 描述了双重隔离。 CMOS器件包括n型场效应晶体管（nFET）区域，nFET区域包括由应变硅组成的一个或多个鳍片，nFET区域中的一个或鳍形成在绝缘体上。 CMOS器件还包括p型场效应晶体管（pFET）区域，pFET区域包括在外延生长的硅上包括硅（Si）或硅锗（SiGe）的一个或多个鳍，并且包括浅沟槽隔离（STI） 填充以将pFET区域中的一个或多个翅片彼此隔离。

公开(公告)号：US20160233240A1

公开(公告)日：2016-08-11

申请号：US14618397

申请日：2015-02-10

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L21/027 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/0276 ,  H01L21/30604 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849

Abstract: A method of forming fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device are described. The method includes forming a strained silicon-on-insulator (SSOI) layer in both a pFET region and an nFET region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pFET region to expose the bulk substrate, epitaxially growing silicon (Si) from the bulk substrate in only the pFET region, and epitaxially growing additional semiconductor material on the Si in only the pFET region. The method also includes forming fins from the additional semiconductor material and a portion of the Si grown on the bulk substrate in the pFET region, and forming fins from the strained silicon layer and the insulator in the nFET region.

公开(公告)号：US20160225770A1

公开(公告)日：2016-08-04

申请号：US15082161

申请日：2016-03-28

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/10 ,  H01L27/12

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming replacement fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor device (nFET) and a CMOS device are described. The method includes forming strained silicon (Si) fins from a strained silicon-on-insulator (SSOI) layer in both an nFET region and a pFET region, forming insulating layers over the strained Si fins, and forming trenches within the insulating layers to expose the strained Si fins in the pFET region only. The method also includes etching the strained Si fins in the pFET region to expose a buried oxide (BOX) layer of the SSOI layer, etching the exposed portions of the BOX layer to expose a bulk substrate, epitaxially growing a Si portion of pFET replacement fins from the bulk substrate, and epitaxially growing silicon germanium (SiGe) portions of the pFET replacement fins on the Si portion of the pFET replacement fins.

Abstract translation: 描述了在包括p型场效应晶体管器件（pFET）和n型场效应晶体管器件（nFET）和CMOS器件的互补金属氧化物半导体（CMOS）器件中形成替换鳍片的方法 。 该方法包括从nFET区域和pFET区域中的应变绝缘体上硅（SSOI）层形成应变硅（Si）鳍，在应变Si散热片上形成绝缘层，并在绝缘层内形成沟槽以暴露 仅在pFET区域中的应变Si散热片。 该方法还包括蚀刻pFET区域中的应变Si散热片以暴露SSOI层的掩埋氧化物（BOX）层，蚀刻BOX层的暴露部分以暴露大块衬底，外延生长pFET替代鳍片的Si部分 并且在pFET替换鳍片的Si部分上外延生长pFET替换鳍片的硅锗（SiGe）部分。

公开(公告)号：US20160111525A1

公开(公告)日：2016-04-21

申请号：US14976867

申请日：2015-12-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/306 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

公开(公告)号：US20160093697A1

公开(公告)日：2016-03-31

申请号：US14874505

申请日：2015-10-05

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Hong He ,  Seth L. Knupp ,  Raghavasimhan Sreenivasan ,  Sean Teehan ,  Allan W. Upham ,  Chih-Chao Yang

IPC: H01L29/12 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/122 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A finFET with a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The structure may include a fin having a {100} crystallographic orientation; a conformal well covering the fin; and a conformal barrier covering the conformal well.

Abstract translation: 具有在{100}晶体取向翅片上具有共形外延阱的量子阱的finFET。 该结构可以包括具有{100}晶体取向的翅片; 覆盖鳍的保形井; 以及覆盖保形井的保形屏障。

公开(公告)号：US09276013B1

公开(公告)日：2016-03-01

申请号：US14601338

申请日：2015-01-21

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/02 ,  H01L21/225 ,  H01L21/324 ,  H01L21/311 ,  H01L21/306 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/66818

Abstract: A method of fabricating silicon (Si) and silicon germanium (SiGe) fins is described. The method includes forming at least two Si fins on a buried oxide (BOX) layer disposed on a substrate, at least one Si fin being formed in a first region and at least one Si fin being formed in a second region, the at least one Si fin in the second region being thinner than the at least one Si fin in the first region. The method also includes depositing an oxide mask over the first region, epitaxially growing an SiGe layer on the at least one Si fin in the second region, and performing a thermal annealing process to drive Ge from the SiGe layer into the at least one Si fin in the second region to form at least one SiGe fin in the second region.

Abstract translation: 描述了制造硅（Si）和硅锗（SiGe）翅片的方法。 该方法包括在设置在衬底上的掩埋氧化物（BOX）层上形成至少两个Si散热片，至少一个Si鳍形成在第一区域中，并且至少一个Si鳍片形成在第二区域中，所述至少一个 第二区域中的Si鳍片比第一区域中的至少一个Si鳍片薄。 该方法还包括在第一区域上沉积氧化物掩模，在第二区域中在至少一个Si鳍片上外延生长SiGe层，并且执行热退火工艺以将Ge从SiGe层驱动到至少一个Si鳍 在第二区域中在第二区域中形成至少一个SiGe鳍。

公开(公告)号：US20150311320A1

公开(公告)日：2015-10-29

申请号：US14584790

申请日：2014-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/225

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

Abstract translation: 一种形成半导体器件的方法，包括在包括鳍结构的硅上形成包括鳍结构的硅并形成含锗层。 然后，锗从含锗层扩散到包括鳍结构的硅中，以将包括鳍结构的硅转化为包括鳍结构的硅锗。

公开(公告)号：US20150255300A1

公开(公告)日：2015-09-10

申请号：US14198005

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/308 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/3085 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

Abstract translation: 一种形成鳍状场效应晶体管器件的方法包括在衬底上形成包括硅的一个或多个第一鳍片，在一个或多个第一鳍片的侧面上形成外延层，以及去除一个或多个第一鳍片以形成 多个第二鳍片。

公开(公告)号：US20150243760A1

公开(公告)日：2015-08-27

申请号：US14191751

申请日：2014-02-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Tenko Yamashita ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66545 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess.

Abstract translation: 一种用于半导体制造的方法包括在衬底的相对侧上提供掩模层，所述衬底具有一个或多个心轴。 沿着掩模层的周边形成虚拟间隔物。 在虚拟间隔件之间形成虚拟栅极结构。 去除虚拟间隔物以提供凹陷。 在凹槽中形成低k间隔物。