公开(公告)号：US12170323B2

公开(公告)日：2024-12-17

申请号：US18365995

申请日：2023-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US20240412991A1

公开(公告)日：2024-12-12

申请号：US18491237

申请日：2023-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-En Lee ,  MingYuan Song ,  Hung-Li Chiang ,  Jer-Fu Wang ,  Chao-Ching Cheng ,  Iuliana Radu

IPC: H01L21/67 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes forming first bonding pads over a first substrate, wherein the first bonding pads include a layer of ferromagnetic material, wherein each first bonding pad produces a respective magnetic field having a first orientation; and bonding second bonding pads to the first bonding pads using metal-to-metal bonding.

公开(公告)号：US20240379440A1

公开(公告)日：2024-11-14

申请号：US18782274

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Ang Chao ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10K10/46 ,  H10K71/12 ,  H10K85/20

Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

公开(公告)号：US12046665B2

公开(公告)日：2024-07-23

申请号：US18160256

申请日：2023-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Chun-Chieh Lu ,  Ming-Yang Li ,  Tzu-Chiang Chen

IPC: H01L29/76 ,  H01L29/04 ,  H01L29/20 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7606 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/454 ,  H01L29/66795 ,  H01L29/785

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

公开(公告)号：US11929425B2

公开(公告)日：2024-03-12

申请号：US17352507

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US11594615B2

公开(公告)日：2023-02-28

申请号：US17216448

申请日：2021-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Yu-Lin Yang ,  Wei-Sheng Yun ,  Chen-Feng Hsu ,  Tzu-Chiang Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/04 ,  H01L29/08 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

公开(公告)号：US11482571B2

公开(公告)日：2022-10-25

申请号：US16908896

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen

IPC: H01L23/538 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

公开(公告)号：US11476356B2

公开(公告)日：2022-10-18

申请号：US16887729

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

公开(公告)号：US20220231153A1

公开(公告)日：2022-07-21

申请号：US17150658

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Tzu Ang Chao ,  Chao-Ching Cheng ,  Lain-Jong Li

IPC: H01L29/76 ,  H01L23/31 ,  H01L27/092 ,  H01L29/24 ,  H01L29/417 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/8256 ,  H01L29/66 ,  H01L27/28 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

Abstract: A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the etch stop layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

公开(公告)号：US11380369B2

公开(公告)日：2022-07-05

申请号：US16427292

申请日：2019-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Yu-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen

IPC: H01L27/11592 ,  G11C5/06 ,  H01L27/1159 ,  G11C11/22 ,  H01L45/00 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/24 ,  H01L27/22 ,  H01L27/11597 ,  G11C11/16

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.