公开(公告)号：US20190355694A1

公开(公告)日：2019-11-21

申请号：US16524146

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/66 ,  H01L21/768 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US10304790B2

公开(公告)日：2019-05-28

申请号：US16226655

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shou-Zen Chang ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Kai-Chiang Wu ,  Ming-Kai Liu

IPC: H01L23/66 ,  H01Q1/24 ,  H01L21/48 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00 ,  H01L23/552 ,  H01L21/56 ,  H01Q1/22 ,  H01L21/60

Abstract: An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor. A method of fabricating the integrated fan-out package is also provided.

公开(公告)号：US20190122978A1

公开(公告)日：2019-04-25

申请号：US16221632

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chun Tang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Che-Wei Hsu

IPC: H01L23/528 ,  H01Q1/22 ,  H01L23/66 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

公开(公告)号：US09355956B2

公开(公告)日：2016-05-31

申请号：US14070105

申请日：2013-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Hao-Hsiang Chuang ,  Jeng-Shien Hsieh ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01F5/00 ,  H01F27/28 ,  H01L23/522 ,  H01F17/00 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01F17/0013 ,  H01F2017/002 ,  H01F2017/0086 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/17 ,  H01L28/10 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive lines is spaced apart from one another. Each of the second conductive lines is spaced apart from one another, and each of the second conductive lines crosses over each of the first conductive lines. Each of the contacts electrically interconnects one of the first conductive lines and one of the second conductive lines. These contacts are arranged in a way such that at least parts of the first conductive lines and at least parts of the second conductive lines form an electric current path serving as an inductor.

Abstract translation: 电感器包括多个第一导电线，多个第二导线和多个触点。 每个第一导线彼此间隔开。 每个第二导线彼此间隔开，并且每个第二导线穿过每个第一导线。 每个触点将第一导线和第二导线之一电连接。 这些触点被布置成使得第一导线的至少一部分和第二导线的至少一部分形成用作电感器的电流路径。

公开(公告)号：US20250087608A1

公开(公告)日：2025-03-13

申请号：US18958345

申请日：2024-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Wei Ling Chang ,  Chieh-Yen Chen ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532

Abstract: In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.

公开(公告)号：US12191270B2

公开(公告)日：2025-01-07

申请号：US17571022

申请日：2022-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Wei Ling Chang ,  Chieh-Yen Chen ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532

Abstract: In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.

公开(公告)号：US12087757B2

公开(公告)日：2024-09-10

申请号：US18344456

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC: H01L25/04 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L22/14 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/32013 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182 ,  H01L2924/35

Abstract: In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

公开(公告)号：US20240258286A1

公开(公告)日：2024-08-01

申请号：US18593536

申请日：2024-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Chieh-Yen Chen

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L2924/12 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

公开(公告)号：US20240142732A1

公开(公告)日：2024-05-02

申请号：US18151015

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsin Lu ,  Chin-Her Chien ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: G02B6/42 ,  G02B6/132

CPC classification number: G02B6/4295 ,  G02B6/132 ,  G02B2006/12061

Abstract: A method includes forming a first waveguide over a substrate; forming a first layer of low-dimensional material on the first waveguide; forming a first layer of dielectric material over the first layer of low-dimensional material; forming a second layer of low dimensional material on the first layer of dielectric material; and forming a first conductive contact that electrically contacts the first layer of low-dimensional material and a second conductive contact that electrically contacts the second layer of low-dimensional material.

公开(公告)号：US11841541B2

公开(公告)日：2023-12-12

申请号：US16882773

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chieh Chang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: G02B6/42 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/16 ,  G02B6/43 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/683

CPC classification number: G02B6/4274 ,  G02B6/4202 ,  G02B6/4239 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/20 ,  H01L25/167 ,  H01L2224/214

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.