公开(公告)号：US20240387502A1

公开(公告)日：2024-11-21

申请号：US18786526

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Tzu-Chun Tang ,  Chuei-Tang Wang

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments provide regulated power routing through various inactive features of a device. In one embodiment, such inactive features include a through via wall which can be formed in an encapsulating material of a die stack. In another embodiment, such inactive features include a heat dissipation features formed over the die stack. In another embodiment, such inactive features include dummy via blocks attached adjacent a die cube. Yet other embodiments may combine the features of these embodiments without limitation.

公开(公告)号：US20240371851A1

公开(公告)日：2024-11-07

申请号：US18773173

申请日：2024-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC: H01L25/00 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

Abstract: In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.

公开(公告)号：US12080684B2

公开(公告)日：2024-09-03

申请号：US17808774

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC: H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/566 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2924/1434

Abstract: A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.

公开(公告)号：US20240241316A1

公开(公告)日：2024-07-18

申请号：US18155131

申请日：2023-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chuei-Tang Wang ,  Chia-Chia Lin ,  Chung-Hao Tsai

IPC: G02B6/13 ,  H01L23/00 ,  H01L25/16 ,  H04B10/50

CPC classification number: G02B6/13 ,  H01L24/08 ,  H01L24/80 ,  H01L25/167 ,  H04B10/50 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: An optical interposer is utilized in order to send and receive signals from external sources such as an optical fiber. The optical interposer receives the signals, routes the signals to various attached components, and when desired, converts the signals between optical and electrical signals. The various attached components may include memory devices such as a high bandwidth memory, processing components, such as an xPU, combinations of these, or the like.

公开(公告)号：US11984668B2

公开(公告)日：2024-05-14

申请号：US17360242

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Monsen Liu ,  Lai Wei Chih ,  Chung-Hao Tsai ,  Jeng-Shien Hsieh ,  En-Hsiang Yeh ,  Chuei-Tang Wang

IPC: H01Q9/04 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/38

CPC classification number: H01Q9/0407 ,  H01L24/19 ,  H01L24/97 ,  H01Q1/38 ,  H01L21/568 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/8203 ,  H01L2224/9222 ,  H01L2924/18162

Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

公开(公告)号：US11948926B2

公开(公告)日：2024-04-02

申请号：US17854386

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Chieh-Yen Chen

IPC: H01L25/16 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L2924/12 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

公开(公告)号：US20240105682A1

公开(公告)日：2024-03-28

申请号：US18526016

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Yih Wang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H10B12/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5283 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H10B12/02 ,  H10B12/315 ,  H10B12/50 ,  H10N50/01 ,  H10N50/80 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

公开(公告)号：US20240088078A1

公开(公告)日：2024-03-14

申请号：US18150034

申请日：2023-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Yih Wang ,  Wei-Ting Chen ,  Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1437

Abstract: Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.

公开(公告)号：US20230352367A1

公开(公告)日：2023-11-02

申请号：US17661622

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chuei-Tang Wang ,  Shih-Chang Ku ,  Chien-Yuan Huang

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/4334 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L2225/1058 ,  H01L2924/182 ,  H01L2225/1023 ,  H01L2225/1094 ,  H01L25/105

Abstract: A device includes a first semiconductor device including a first bonding layer; a second semiconductor device bonded to the first bonding layer of the first semiconductor device; thermal structures disposed beside the second semiconductor device and on the first bonding layer, wherein the thermal structures include a conductive material, wherein the thermal structures are electrically isolated from the first semiconductor device and from the second semiconductor device; an encapsulant disposed on the first bonding layer, wherein the encapsulant surrounds the second semiconductor device and surrounds the thermal structures; and a second bonding layer disposed over the encapsulant, the thermal structures, and the second semiconductor device.

公开(公告)号：US20230253384A1

公开(公告)日：2023-08-10

申请号：US18301555

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L25/162 ,  H01L21/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/20 ,  H01L25/16 ,  H01L25/105 ,  H01G4/00 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08225 ,  H01L2224/16235 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/15313 ,  H01L2924/19011 ,  H01L2924/19105

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.