公开(公告)号：US09184234B2

公开(公告)日：2015-11-10

申请号：US14156546

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yuan Chen ,  Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/36 ,  H01L29/16 ,  H01L29/165 ,  H01L21/02 ,  H01L21/265 ,  H01L29/167

CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type.

Abstract translation: 本公开的一些实施例涉及形成在包含第一杂质类型的掺杂杂质的半导体衬底中的晶体管器件。 该晶体管器件包括由包括第一杂质类型的掺杂杂质的δ掺杂层构成的沟道，并且被配置为在沟道内产生峰值掺杂剂浓度。 通道还包括覆盖在δ掺杂层上的含碳材料层，并且被配置为防止掺杂剂从δ-掺杂层和半导体衬底的反向扩散。 通道还包括覆盖在含碳材料层上的衬底材料层，并且被配置为在通道的表面附近实现陡峭的逆向掺杂剂浓度分布。 在一些实施例中，反掺杂层位于配置成减少半导体衬底内的泄漏的δ掺杂层的下面，并且包括与第一杂质类型相反的第二杂质类型的掺杂杂质。

公开(公告)号：US20150162445A1

公开(公告)日：2015-06-11

申请号：US14100263

申请日：2013-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract translation: IC的性能提升和几何尺寸的需求引起了包括finFET器件在内的多栅极器件的引入。 在区域中诱导更高的拉伸应变/应力提供增强的电子迁移率，这可以提高性能。 器件制造期间的高温工艺往往会使这些应变诱导层的应力松弛。 本公开涉及在finFET器件形成工艺的RPG（替代多晶硅栅极）级形成应变诱导层或覆盖层的方法。 在一些实施例中，应变诱导层被掺杂以减小外部电阻。

公开(公告)号：US12302640B2

公开(公告)日：2025-05-13

申请号：US18355895

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H10D87/00 ,  H01L21/762 ,  H10D30/62 ,  H10D30/67 ,  H10D62/10 ,  H10D62/17 ,  H10D62/40 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D86/00 ,  H10D86/01

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US12217782B2

公开(公告)日：2025-02-04

申请号：US18332674

申请日：2023-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  Yih Wang

IPC: G11C11/16

Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

公开(公告)号：US20240379593A1

公开(公告)日：2024-11-14

申请号：US18771809

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Wen-Chiung Tu ,  Yuan-Yang Hsiao ,  Kai Tak Lam ,  Chen-Chiu Huang ,  Zhiqiang Wu ,  Dian-Hau Chen

IPC: H01L23/00

Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.

公开(公告)号：US12087714B2

公开(公告)日：2024-09-10

申请号：US17589500

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Wen-Chiung Tu ,  Yuan-Yang Hsiao ,  Kai Tak Lam ,  Chen-Chiu Huang ,  Zhiqiang Wu ,  Dian-Hau Chen

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/35121

Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.

公开(公告)号：US20230411399A1

公开(公告)日：2023-12-21

申请号：US18355895

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L29/045 ,  H01L21/823821 ,  H01L21/823807 ,  H01L21/76275 ,  H01L21/76283 ,  H01L27/1211 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/7869 ,  H01L29/1033 ,  H01L29/785 ,  H01L21/823878 ,  H01L29/7853 ,  H01L27/0924

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US20230123846A1

公开(公告)日：2023-04-20

申请号：US18066373

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a stack of first semiconductor layers and second semiconductor layers over a substrate, etching the stack to form a source/drain (S/D) recess in exposing the substrate, and forming an S/D formation assistance region in the S/D recess. The S/D formation assistance region is partially embedded in the substrate and includes a semiconductor seed layer embedded in an isolation layer. The isolation layer electrically isolates the semiconductor seed layer from the substrate. The method also includes epitaxially growing an S/D feature in the S/D recess from the semiconductor seed layer. The S/D feature is in physical contact with the second semiconductor layers.

公开(公告)号：US11616151B2

公开(公告)日：2023-03-28

申请号：US17206646

申请日：2021-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Zhiqiang Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

公开(公告)号：US11557659B2

公开(公告)日：2023-01-17

申请号：US17170263

申请日：2021-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chia-Ying Su ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234

Abstract: Embodiments of the present disclosure includes a method of forming a semiconductor device. The method includes providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate. The method also includes patterning the first semiconductor layers and the second semiconductor layers to form a first fin and a second fin, removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin, and doping a threshold modifying impurity into the first suspended nanostructures in the first fin.