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公开(公告)号：US20240198455A1
公开(公告)日：2024-06-20
申请号：US18589527
申请日：2024-02-28
发明人： Kuo-Ming Wu , Yung-Lung Lin , Hau-Yi Hsiao , Sheng-Chau Chen , Cheng-Yuan Tsai
IPC分类号： B23K26/361 , B23K26/035 , B23K26/062 , H01L21/02 , H01L21/66
CPC分类号： B23K26/361 , B23K26/035 , B23K26/062 , H01L21/02021 , H01L22/10
摘要： In some embodiments, the present disclosure relates to a method of trimming an annular portion of a wafer. The method includes aligning the wafer over a wafer chuck. The method uses a rotating blade having a first rotational speed to remove the annular portion from an upper surface of the wafer. While the rotating blade is removing the annular portion of the upper surface of the wafer, measuring a parameter of the wafer at a position adjacent to the rotating blade. Lastly, the method involves changing the first rotation speed of the rotating blade to a second rotational speed when the parameter is greater than a predetermined threshold.
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公开(公告)号：US20240079268A1
公开(公告)日：2024-03-07
申请号：US18506186
申请日：2023-11-10
IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L23/522 , H01L23/528 , H01L25/00 , H01L25/065
CPC分类号： H01L21/76834 , H01L21/76822 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/80986
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.
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公开(公告)号：US20230354613A1
公开(公告)日：2023-11-02
申请号：US18340933
申请日：2023-06-26
发明人： Bi-Shen Lee , Tzu-Yu Lin , Yi-Yang Wei , Hai-Dang Trinh , Hsun-Chung Kuang , Cheng-Yuan Tsai
摘要： In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
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公开(公告)号：US20230299105A1
公开(公告)日：2023-09-21
申请号：US18324206
申请日：2023-05-26
发明人： Sheng-Chan Li , Cheng-Hsien Chou , Cheng-Yuan Tsai , Keng-Yu Chou , Yeur-Luen Tu
IPC分类号： H01L27/146
CPC分类号： H01L27/14629 , H01L27/14607
摘要： The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a pixel region arranged between one or more trenches formed by sidewalls of the substrate. One or more dielectric materials are arranged along the sidewalls of the substrate forming the one or more trenches. A conductive material is disposed within the one or more trenches. The conductive material is electrically coupled to an interconnect disposed within a dielectric arranged on the substrate.
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公开(公告)号：US20230276721A1
公开(公告)日：2023-08-31
申请号：US18313475
申请日：2023-05-08
发明人： Hai-Dang Trinh , Cheng-Yuan Tsai , Hsing-Lien Lin , Wen-Ting Chu
CPC分类号： H10N70/801 , G06F12/0246 , H10N70/021 , H10N70/24 , H10N70/061 , H10N70/063 , H10N70/826 , H10N70/881 , H10N70/8833 , H10N70/8836 , H10B63/30
摘要： The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes a first metal and a second metal. The first metal has a peak concentration at a first distance from the first electrode and the second metal has a peak concentration at a second distance from the first electrode. The first distance is different than the second distance.
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公开(公告)号：US20230275064A1
公开(公告)日：2023-08-31
申请号：US18311304
申请日：2023-05-03
IPC分类号： H01L23/00 , H01L21/02 , H01L21/67 , H01L23/544 , H01L25/065
CPC分类号： H01L24/94 , H01L21/02164 , H01L21/67121 , H01L23/544 , H01L24/80 , H01L25/0657 , H01L2224/80132 , H01L2224/80007 , H01L2224/80895 , H01L2224/80896
摘要： Various embodiments of the present disclosure are directed towards a processing tool. The processing tool includes a housing structure defining a chamber. A first plate is disposed in the chamber. A first plasma exclusion zone (PEZ) ring is disposed on the first plate. A second plate is disposed in the chamber and underlies the first plate. A second PEZ ring is disposed on the second plate. The second PEZ ring comprises a PEZ ring notch that extends inwardly from a circumferential edge of the second PEZ ring.
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公开(公告)号：US11716913B2
公开(公告)日：2023-08-01
申请号：US17718424
申请日：2022-04-12
发明人： Hai-Dang Trinh , Chii-Ming Wu , Cheng-Yuan Tsai , Tzu-Chung Tsai , Fa-Shen Jiang
CPC分类号： H10N70/826 , H10N70/021 , H10N70/063 , H10N70/8833 , H10N70/8836 , H10N70/231
摘要： Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a lower conductive structure over a substrate. A data storage structure is formed on the lower conductive structure. A bandgap of the data storage structure discretely increases or decreases at least two times from a top surface of the data storage structure in a direction towards the substrate. An upper conductive structure is formed on the data storage structure.
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公开(公告)号：US11670584B2
公开(公告)日：2023-06-06
申请号：US17444334
申请日：2021-08-03
发明人： Chen-Fa Lu , Cheng-Yuan Tsai , Ching-Chung Hsu , Chung-Long Chang
IPC分类号： H01L29/00 , H01L23/522 , H01L23/532 , H01L21/027 , H01L21/288 , H01L21/311 , H01L21/768 , H01L23/31 , H01L23/528
CPC分类号： H01L23/5227 , H01L21/0273 , H01L21/288 , H01L21/31144 , H01L21/7684 , H01L21/76802 , H01L21/76879 , H01L23/3171 , H01L23/5226 , H01L23/5283 , H01L23/5329 , H01L23/53238 , H01L23/53295 , H01L2224/11
摘要： The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.
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公开(公告)号：US20220077385A1
公开(公告)日：2022-03-10
申请号：US17528574
申请日：2021-11-17
摘要： Some embodiments relate to an integrated chip. The integrated chip includes a memory cell over a substrate, where the memory cell comprises a data storage structure. A conductive interconnect is over the data storage structure and comprises a first protrusion adjacent to a first side of the data storage structure, where the first protrusion comprises a flat bottom surface. A spacer structure is disposed on the first side of the data storage structure. The spacer structure directly contacts the flat bottom surface of the first protrusion.
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公开(公告)号：US11257997B2
公开(公告)日：2022-02-22
申请号：US16732222
申请日：2019-12-31
发明人： Chia-Hua Lin , Yao-Wen Chang , Chii-Ming Wu , Cheng-Yuan Tsai , Eugene I-Chun Chen , Tzu-Chung Tsai
摘要： A semiconductor structure is provided. The semiconductor structure includes metallization structure, a plurality of conductive pads, and a dielectric layer. The plurality of conductive pads is over the metallization structure. The dielectric layer is on the metallization structure and covers the conductive pad. The dielectric layer includes a first dielectric film, a second dielectric film, and a third dielectric film. The first dielectric film is on the conductive pad. The second dielectric film is on the first dielectric film. The third dielectric film is on the second dielectric film. The a refractive index of the first dielectric film is smaller than a refractive index of the second dielectric film, and the refractive index of the second dielectric film is smaller than a refractive index of the third dielectric film.
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